[PATCH 53/53] drm/i915/dg2: Configure PCON in DP pre-enable path

[Matt Roper]

From: Ankit Nautiyal <ankit.k.nauti...@intel.com>

Add the functions to configure HDMI2.1 pcon for DG2, before DP link
training.

Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5499a2975a0e..77f79f3269a1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2580,6 +2580,7 @@ static void dg2_ddi_pre_enable_dp(struct 
intel_atomic_state *state,
        if (!is_mst)
                intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
 
+       intel_dp_configure_protocol_converter(intel_dp, crtc_state);
        intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
        /*
         * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
@@ -2587,6 +2588,8 @@ static void dg2_ddi_pre_enable_dp(struct 
intel_atomic_state *state,
         * training
         */
        intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
+       intel_dp_check_frl_training(intel_dp);
+       intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
 
        /*
         * 5.h Follow DisplayPort specification training sequence (see notes for
-- 
2.25.4