> Am 09.11.2021 um 21:36 schrieb Paul Cercueil <p...@crapouillou.net>:
>
> Hi Nikolaus,
>
> Le mar., nov. 9 2021 at 21:19:17 +0100, H. Nikolaus Schaller
> <h...@goldelico.com> a écrit :
>> Hi Paul,
>>> Am 07.11.2021 um 20:05 schrieb Paul Cercueil <p...@crapouillou.net>:
>>>> 6. Therefore I think it *may* work overclocked with 48MHz
>>>> but is not guaranteed or reliable above 27 MHz.
>>>> So everything is ok here.
>>> One thing though - the "assigned-clocks" and "assigned-clock-rates", while
>>> it works here, should be moved to the CGU node, to respect the YAML schemas.
>> Trying to do this seems to break boot.
>> I can boot up to
>> [ 8.312926] dw-hdmi-ingenic 10180000.hdmi: registered DesignWare HDMI I2C
>> bus driver
>> and
>> [ 11.366899] [drm] Initialized ingenic-drm 1.1.0 20200716 for
>> 13050000.lcdc0 on minor 0
>> but then the boot process becomes slow and hangs. Last sign of activity is
>> [ 19.347659] hub 1-0:1.0: USB hub found
>> [ 19.353478] hub 1-0:1.0: 1 port detected
>> [ 32.321760] wlan0_power: disabling
>> What I did was to just move
>> assigned-clocks = <&cgu JZ4780_CLK_HDMI>;
>> assigned-clock-rates = <27000000>;
>> from
>> hdmi: hdmi@10180000 {
>> to
>> cgu: jz4780-cgu@10000000 {
>> Does this mean the clock is assigned too early or too late?
>> Do you have any suggestions since I don't know the details of CGU.
>
> These properties are already set for the CGU node in ci20.dts:
Ah, I didn't look into that. Maybe because I thought adding this should stay in
jz4780.dtsi to be available for any board making use of it.
So it gets overwritten and is then completely missing.
>
> &cgu {
> /*
> * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
> * precision.
> */
> assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>;
> assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>;
> assigned-clock-rates = <48000000>;
> };
>
> So you want to update these properties to add the HDMI clock setting, like
> this:
>
> assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>,
> <&cgu JZ4780_CLK_HDMI>;
> assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>;
> assigned-clock-rates = <48000000>, <0>, <27000000>;
Will give it a try.
I would prefer if it could sit in jz4780.dtsi and ci20.dts would just extend it
but IMHO this is beyond DTS capabilities.
So we likely have to live with that.
BR and thanks,
Nikolaus
