On Thu, Mar 03, 2022 at 02:37:35PM -0800, john.c.harri...@intel.com wrote:
> From: John Harrison <john.c.harri...@intel.com>
>
> An earlier patch added support for compute engines. However, it missed
> enabling the anti-pre-emption w/a for the new engine class. So move
> the 'compute capable' flag earlier and use it for the pre-emption w/a
> test.
>
> Fixes: c674c5b9342e ("drm/i915/xehp: CCS should use RCS setup functions")
> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
> Cc: Aravind Iddamsetty <aravind.iddamse...@intel.com>
> Cc: Matt Roper <matthew.d.ro...@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
> Cc: Daniel Vetter <daniel.vet...@ffwll.ch>
> Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
> Cc: Lucas De Marchi <lucas.demar...@intel.com>
> Cc: John Harrison <john.c.harri...@intel.com>
> Cc: Jason Ekstrand <ja...@jlekstrand.net>
> Cc: "Michał Winiarski" <michal.winiar...@intel.com>
> Cc: Matthew Brost <matthew.br...@intel.com>
> Cc: Chris Wilson <ch...@chris-wilson.co.uk>
> Cc: Tejas Upadhyay <tejaskumarx.surendrakumar.upadh...@intel.com>
> Cc: Umesh Nerlige Ramappa <umesh.nerlige.rama...@intel.com>
> Cc: "Thomas Hellström" <thomas.hellst...@linux.intel.com>
> Cc: Stuart Summers <stuart.summ...@intel.com>
> Cc: Matthew Auld <matthew.a...@intel.com>
> Cc: Jani Nikula <jani.nik...@intel.com>
> Cc: Ramalingam C <ramalinga...@intel.com>
> Cc: Akeem G Abodunrin <akeem.g.abodun...@intel.com>
> Signed-off-by: John Harrison <john.c.harri...@intel.com>
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 22e70e4e007c..4185c7338581 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -421,6 +421,12 @@ static int intel_engine_setup(struct intel_gt *gt, enum
> intel_engine_id id,
> engine->logical_mask = BIT(logical_instance);
> __sprint_engine_name(engine);
>
> + /* features common between engines sharing EUs */
> + if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
> + engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
> + engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
> + }
> +
> engine->props.heartbeat_interval_ms =
> CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
> engine->props.max_busywait_duration_ns =
> @@ -433,15 +439,9 @@ static int intel_engine_setup(struct intel_gt *gt, enum
> intel_engine_id id,
> CONFIG_DRM_I915_TIMESLICE_DURATION;
>
> /* Override to uninterruptible for OpenCL workloads. */
> - if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
> + if (GRAPHICS_VER(i915) == 12 && (engine->flags &
> I915_ENGINE_HAS_RCS_REG_STATE))
> engine->props.preempt_timeout_ms = 0;
>
> - /* features common between engines sharing EUs */
> - if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
> - engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
> - engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
> - }
> -
> /* Cap properties according to any system limits */
> #define CLAMP_PROP(field) \
> do { \
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
