On Fri, 3 Jun 2022 at 04:02, Jessica Zhang <quic_jessz...@quicinc.com> wrote: > On 6/2/2022 3:51 PM, Dmitry Baryshkov wrote: > > On 28/05/2022 01:23, Jessica Zhang wrote: > >> On 5/27/2022 12:46 PM, Dmitry Baryshkov wrote: > >>> On 27/05/2022 21:54, Jessica Zhang wrote: > >>>> Add support for writing CRC values for the interface block to > >>>> the debugfs by calling the necessary MISR setup/collect methods. > >>>> > >>>> Signed-off-by: Jessica Zhang <quic_jessz...@quicinc.com>
[skipped] > >>>> + > >>>> + phys->hw_intf->ops.setup_misr(phys->hw_intf, true, 1); > >>>> + } > >>>> +} > >>>> + > >>>> +int dpu_encoder_get_crc(const struct drm_encoder *drm_enc) > >>>> +{ > >>>> + struct dpu_encoder_virt *dpu_enc; > >>>> + u32 crcs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; > >>>> + > >>>> + int i, rc; > >>>> + > >>>> + if (!drm_enc->crtc) { > >>>> + DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index); > >>>> + return -EINVAL; > >>>> + } > >>>> + > >>>> + dpu_enc = to_dpu_encoder_virt(drm_enc); > >>>> + > >>>> + for (i = 0; i < dpu_enc->num_phys_encs; i++) { > >>>> + struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; > >>>> + > >>>> + if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr) > >>>> + continue; > >>>> + > >>>> + rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[i]); > >>> > >>> This doesn't look fully correct. Do we need to skip the indices for > >>> the phys without a backing hw_intf? > >> > >> Sorry if I'm misunderstanding your question, but don't we need to have > >> a backing hw_intf (and skip if there isn't any) since the methods for > >> collecting/setting MISR registers is within the hw_intf? > > > > Yes. So the question if we should skip the phys and leave the crcs[i] > > untouched, skip the phys and sset crcs[i] to 0 or change > > dpu_crtc_parse_crc_source() to return the number of intf-backed > > phys_enc's and do not skip any crcs[i]. > > Thanks for the clarification. > > Is it possible to hit a case where a phys_encoder won't have a > corresponding hw_intf? > > AFAIK, it seems guaranteed that a phys_encoder will have an hw_intf > since dpu_encoder_setup_display will skip incrementing num_phys_encs if > dpu_encoder_get_intf fails [1]. WB encoders won't have hw_intf. The code checks that either get_intf or get_wb succeeds. > > [1] > https://gitlab.freedesktop.org/drm/msm/-/blob/msm-next/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c#L2263 -- With best wishes Dmitry