Reviewed-by: Caz Yokoyama <c...@caztech.com>
-caz
On Fri, Jun 24, 2022 at 2:04 PM Matt Roper <matthew.d.ro...@intel.com>
wrote:
> We've been introducing new registers with a mix of "XEHP_"
> (architecture) and "XEHPSDV_" (platform) prefixes. For consistency,
> let's settle on "XEHP_" as the preferred form.
>
> XEHPSDV_RP_STATE_CAP stays with its current name since that's truly a
> platform-specific register and not something that applies to the Xe_HP
> architecture as a whole.
>
> Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 ++++----
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_region_lmem.c | 8 ++++----
> drivers/gpu/drm/i915/i915_reg.h | 6 +++---
> 5 files changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index e63de9c06596..166d0a4b9e8c 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -836,8 +836,8 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private
> *i915, u16 type,
> } else {
> resource_size_t lmem_range;
>
> - lmem_range = intel_gt_mcr_read_any(&i915->gt0,
> XEHPSDV_TILE0_ADDR_RANGE) & 0xFFFF;
> - lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;
> + lmem_range = intel_gt_mcr_read_any(&i915->gt0,
> XEHP_TILE0_ADDR_RANGE) & 0xFFFF;
> + lmem_size = lmem_range >> XEHP_TILE_LMEM_RANGE_SHIFT;
> lmem_size *= SZ_1G;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 61815b6e87de..37c1095d8603 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -324,11 +324,11 @@
>
> #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
>
> -#define XEHPSDV_TILE0_ADDR_RANGE _MMIO(0x4900)
> -#define XEHPSDV_TILE_LMEM_RANGE_SHIFT 8
> +#define XEHP_TILE0_ADDR_RANGE _MMIO(0x4900)
> +#define XEHP_TILE_LMEM_RANGE_SHIFT 8
>
> -#define XEHPSDV_FLAT_CCS_BASE_ADDR _MMIO(0x4910)
> -#define XEHPSDV_CCS_BASE_SHIFT 8
> +#define XEHP_FLAT_CCS_BASE_ADDR _MMIO(0x4910)
> +#define XEHP_CCS_BASE_SHIFT 8
>
> #define GAMTARBMODE _MMIO(0x4a08)
> #define ARB_MODE_BWGTLB_DISABLE (1 << 9)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> index ae8a8f725f01..73a8b46e0234 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> @@ -679,7 +679,7 @@ static ssize_t media_RP0_freq_mhz_show(struct device
> *dev,
> u32 val;
> int err;
>
> - err = snb_pcode_read_p(gt->uncore, XEHPSDV_PCODE_FREQUENCY_CONFIG,
> + err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
> PCODE_MBOX_FC_SC_READ_FUSED_P0,
> PCODE_MBOX_DOMAIN_MEDIAFF, &val);
>
> @@ -700,7 +700,7 @@ static ssize_t media_RPn_freq_mhz_show(struct device
> *dev,
> u32 val;
> int err;
>
> - err = snb_pcode_read_p(gt->uncore, XEHPSDV_PCODE_FREQUENCY_CONFIG,
> + err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
> PCODE_MBOX_FC_SC_READ_FUSED_PN,
> PCODE_MBOX_DOMAIN_MEDIAFF, &val);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index 2ff448047020..d09b996a9759 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -105,12 +105,12 @@ static struct intel_memory_region *setup_lmem(struct
> intel_gt *gt)
> resource_size_t lmem_range;
> u64 tile_stolen, flat_ccs_base;
>
> - lmem_range = intel_gt_mcr_read_any(&i915->gt0,
> XEHPSDV_TILE0_ADDR_RANGE) & 0xFFFF;
> - lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;
> + lmem_range = intel_gt_mcr_read_any(&i915->gt0,
> XEHP_TILE0_ADDR_RANGE) & 0xFFFF;
> + lmem_size = lmem_range >> XEHP_TILE_LMEM_RANGE_SHIFT;
> lmem_size *= SZ_1G;
>
> - flat_ccs_base = intel_gt_mcr_read_any(gt,
> XEHPSDV_FLAT_CCS_BASE_ADDR);
> - flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT)
> * SZ_64K;
> + flat_ccs_base = intel_gt_mcr_read_any(gt,
> XEHP_FLAT_CCS_BASE_ADDR);
> + flat_ccs_base = (flat_ccs_base >> XEHP_CCS_BASE_SHIFT) *
> SZ_64K;
>
> /* FIXME: Remove this when we have small-bar enabled */
> if (pci_resource_len(pdev, 2) < lmem_size) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index cf5e16abf6c7..643d7f020a4a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6767,12 +6767,12 @@
> #define DG1_UNCORE_GET_INIT_STATUS 0x0
> #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
> #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
> -#define XEHPSDV_PCODE_FREQUENCY_CONFIG 0x6e /*
> xehpsdv, pvc */
> -/* XEHPSDV_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
> +#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */
> +/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
> #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
> #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
> /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
> -/* XEHPSDV_PCODE_FREQUENCY_CONFIG param2 */
> +/* XEHP_PCODE_FREQUENCY_CONFIG param2 */
> #define PCODE_MBOX_DOMAIN_NONE 0x0
> #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
> #define GEN6_PCODE_DATA _MMIO(0x138128)
> --
> 2.36.1
>
>
--
-caz, caz at caztech dot com, 503-six one zero - five six nine nine(m)
