Hi, On Fri, Jul 8, 2022 at 11:00 PM Akhil P Oommen <quic_akhi...@quicinc.com> wrote: > > Update gpu register array with gpucc memory region. > > Signed-off-by: Akhil P Oommen <quic_akhi...@quicinc.com> > --- > > (no changes since v1) > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi > b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index e66fc67..defdb25 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -2228,10 +2228,12 @@ > compatible = "qcom,adreno-635.0", "qcom,adreno"; > reg = <0 0x03d00000 0 0x40000>, > <0 0x03d9e000 0 0x1000>, > - <0 0x03d61000 0 0x800>; > + <0 0x03d61000 0 0x800>, > + <0 0x03d90000 0 0x2000>; > reg-names = "kgsl_3d0_reg_memory", > "cx_mem", > - "cx_dbgc"; > + "cx_dbgc", > + "gpucc";
This doesn't seem right. Shouldn't you be coordinating with the existing gpucc instead of reaching into its registers? -Doug
