Hi Maxime, W dniu 9.09.2022 o 16:00, Maxime Ripard pisze: > On Wed, Sep 07, 2022 at 11:31:21PM +0200, Mateusz Kwiatkowski wrote: >> The "canonical" modelines (at least for vc4's VEC, see the notes below): >> >> - (vfp==4, vsync==6, vbp==39) for 576i >> - (vfp==7, vsync==6, vbp==32) for 480i >> - (vfp==5, vsync==6, vbp==28) for 486i (full frame NTSC as originally >> specified) > > It's not clear to me either how you come up with those timings?
Well, experimentally ;) The values for 480i and 576i are the values currently used by the downstream kernel, and those in turn has been copied from the firmware (or more precisely, I chose them so that the PV registers end up the same as the values set by the firmware). I also checked with an oscilloscope that the waveforms look as they should. VEC doesn't exactly handle the half-lines at the start and end of the odd field right, but otherwise, the blanking and sync pulses are where they should be. The 486i values has been constructed from the 480i ones according to the calculations from cross-referencing SMPTE documents, see my previous e-mail. I know this is perhaps unsatisfactory ;) I don't have access to the VC4 documentation, so this was _almost_ reverse engineering for me. Best regards, Mateusz Kwiatkowski
