Il 12/10/22 21:12, Justin Green ha scritto:
Tested on MT8195 and confirmed both correct video output and improved DRAM
bandwidth performance.
v3:
* Replaced pitch bitshift math with union based approach.
* Refactored overlay register writes to shared code between non-AFBC and
AFBC.
* Minor code cleanups.
v2:
* Marked mtk_ovl_set_afbc as static.
* Reflowed some lines to fit column limit.
Signed-off-by: Justin Green <greenjus...@chromium.org>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 90 +++++++++++++++++++++++-
drivers/gpu/drm/mediatek/mtk_drm_plane.c | 37 +++++++++-
drivers/gpu/drm/mediatek/mtk_drm_plane.h | 8 +++
3 files changed, 131 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 002b0f6cae1a..3f89b5f5064f 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
..snip..
@@ -335,9 +396,10 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int
idx,
addr += pending->pitch - 1;
}
+ mtk_ovl_set_afbc(dev, cmdq_pkt, idx, is_afbc);
I'm sorry for not noticing that in the previous review - there's only one
more issue here: I'm not sure that *all* of the MediaTek chips have the
AFBC bits in OVL_DATAPATH_CON... this may be clashing with something else
in the layout of (very?) old chips.
The solution is simple here. Please, guard this call with:
if (ovl->data->supports_afbc)
mtk_ovl_set_afbc(dev, cmdq_pkt, idx, is_afbc);
...after which
Reviewed-by: AngeloGioacchino Del Regno
<angelogioacchino.delre...@collabora.com>
Cheers!
Angelo
