On Mon, Oct 31, 2022 at 06:15:09AM -0700, Wayne Boyer wrote: > WA 18017747507 applies to all DG2 skus. > > BSpec: 56035, 46121, 68173 > > Signed-off-by: Wayne Boyer <wayne.bo...@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index f4624262dc81..27b2641e1a53 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -501,6 +501,9 @@ > #define VF_PREEMPTION _MMIO(0x83a4) > #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0) > > +#define VFG_PREEMPTION_CHICKEN _MMIO(0x83b4) > +#define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4)
We need one more space here between 'define' and the register name for consistency with the rest of the file. But I can fix that up while applying. Reviewed-by: Matt Roper <matthew.d.ro...@intel.com> Applied to drm-intel-gt-next. Thanks for the patch. Matt > + > #define GEN8_RC6_CTX_INFO _MMIO(0x8504) > > #define XEHP_SQCM MCR_REG(0x8724) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 2a35e7e66625..3cdf5c24dbc5 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -2975,6 +2975,9 @@ general_render_compute_wa_init(struct intel_engine_cs > *engine, struct i915_wa_li > * Wa_22015475538:dg2 > */ > wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); > + > + /* Wa_18017747507:dg2 */ > + wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, > POLYGON_TRIFAN_LINELOOP_DISABLE); > } > } > > -- > 2.37.3 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
