Add new struture to store FRL related configurations for a pipe.
These members to be calculated during compute config phase, when FRL
mode is to be used.
Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
.../drm/i915/display/intel_display_types.h | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index e57fac00e945..8cab50d5d565 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1307,6 +1307,29 @@ struct intel_crtc_state {
u16 flipline, vmin, vmax, guardband;
} vrr;
+ struct {
+ /* Go for FRL training */
+ bool enable;
+
+ /* Enable resource based scheduling */
+ bool rsrc_sched_en;
+
+ /* can be either 3 or 4 lanes */
+ u8 required_lanes;
+
+ /* required rate - can be 3, 6, 8, 10, 12 Gbps */
+ u8 required_rate;
+
+ /* FRL DFM Parameters */
+ u32 tb_borrowed, tb_actual, tb_threshold_min,
active_char_buf_threshold;
+
+ /* FRL DFM DSC Tribytes */
+ u32 hcactive_tb, hctotal_tb;
+
+ /* Clock parameters in KHz */
+ u32 div18, link_m_ext, link_n_ext;
+ } frl;
+
/* Stream Splitter for eDP MSO */
struct {
bool enable;
--
2.25.1
