On 2022-12-12 10:33:13, Konrad Dybcio wrote:
> Years after the SoC support has been added, it's high time for it to
> get dispcc going. Add the node to ensure that.
>
> Signed-off-by: Konrad Dybcio <konrad.dyb...@linaro.org>
On Sony Xperia 5:
Tested-by: Marijn Suijten <marijn.suij...@somainline.org>
Reviewed-by: Marijn Suijten <marijn.suij...@somainline.org>
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index a0c57fb798d3..ff04397777f4 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -3579,6 +3579,32 @@ camnoc_virt: interconnect@ac00000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + dispcc: clock-controller@af00000 {
> + compatible = "qcom,sm8150-dispcc";
> + reg = <0 0x0af00000 0 0x10000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>;
> + clock-names = "bi_tcxo",
> + "dsi0_phy_pll_out_byteclk",
> + "dsi0_phy_pll_out_dsiclk",
> + "dsi1_phy_pll_out_byteclk",
> + "dsi1_phy_pll_out_dsiclk",
> + "dp_phy_pll_link_clk",
> + "dp_phy_pll_vco_div_clk";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> +
> + power-domains = <&rpmhpd SM8150_MMCX>;
> + /* TODO: Maybe rpmhpd_opp_min_svs could work as well? */
Is this still something we want to check/test? Do we need a reference
manual to be sure?
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,sm8150-pdc", "qcom,pdc";
> reg = <0 0x0b220000 0 0x400>;
> --
> 2.38.1
>
