28.11.2022 18:23, Luca Ceresoli пишет:
> +static int tegra20_vip_start_streaming(struct tegra_vip_channel *vip_chan)
> +{
> + struct tegra_vi_channel *vi_chan =
> v4l2_get_subdev_hostdata(&vip_chan->subdev);
> + int width = vi_chan->format.width;
> + int height = vi_chan->format.height;
> +
> + unsigned int main_input_format;
> + unsigned int yuv_input_format;
> +
> + tegra20_vi_get_input_formats(vi_chan, &main_input_format,
> &yuv_input_format);
> +
> + tegra20_vi_write(vi_chan, TEGRA_VI_VI_CORE_CONTROL, 0);
> +
> + tegra20_vi_write(vi_chan, TEGRA_VI_VI_INPUT_CONTROL,
> + VI_INPUT_VIP_INPUT_ENABLE | main_input_format |
> yuv_input_format);
> +
> + tegra20_vi_write(vi_chan, TEGRA_VI_V_DOWNSCALE_CONTROL, 0);
> + tegra20_vi_write(vi_chan, TEGRA_VI_H_DOWNSCALE_CONTROL, 0);
> +
> + tegra20_vi_write(vi_chan, TEGRA_VI_VIP_V_ACTIVE, height <<
> VI_VIP_V_ACTIVE_PERIOD_SFT);
> + tegra20_vi_write(vi_chan, TEGRA_VI_VIP_H_ACTIVE,
> + roundup(width, 2) << VI_VIP_H_ACTIVE_PERIOD_SFT);
> +
> + /*
> + * For VIP, D9..D2 is mapped to the video decoder's P7..P0.
> + * Disable/mask out the other Dn wires. When not in BT656
> + * mode we also need the V/H sync.
> + */
> + tegra20_vi_write(vi_chan, TEGRA_VI_PIN_INPUT_ENABLE,
> + GENMASK(9, 2) << VI_PIN_INPUT_VD_SFT |
> + VI_PIN_INPUT_HSYNC | VI_PIN_INPUT_VSYNC);
> + tegra20_vi_write(vi_chan, TEGRA_VI_VI_DATA_INPUT_CONTROL,
> + GENMASK(9, 2) << VI_DATA_INPUT_SFT);
> + tegra20_vi_write(vi_chan, TEGRA_VI_PIN_INVERSION, 0);
> +
> + tegra20_vi_write(vi_chan, TEGRA_VI_CONT_SYNCPT_OUT_1,
> + VI_CONT_SYNCPT_OUT_1_CONTINUOUS_SYNCPT |
> + host1x_syncpt_id(vi_chan->out_sp) <<
> VI_CONT_SYNCPT_OUT_1_SYNCPT_IDX_SFT);
Wondering whether you also need to set up the sypct_incr condition to
op_done, it should be immediate by default. I see that T210 VI code sets
up the incr condition.
