Remove dpu_hw_fmt_layout instance from struct dpu_hw_sspp_cfg, leaving
only src_rect and dst_rect. This way all the pipes used by the plane
will have a common layout instance (as the framebuffer is shared between
them), while still keeping a separate src/dst rectangle configuration
for each pipe.

Reviewed-by: Abhinav Kumar <quic_abhin...@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 32 ++++++++++-----------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h |  6 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c   | 10 +++----
 3 files changed, 23 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index ab95f2817378..e87c6377f315 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -490,7 +490,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe 
*pipe,
 }
 
 static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
-               struct dpu_hw_sspp_cfg *cfg)
+               struct dpu_hw_fmt_layout *layout)
 {
        struct dpu_hw_sspp *ctx = pipe->sspp;
        u32 ystride0, ystride1;
@@ -501,41 +501,41 @@ static void dpu_hw_sspp_setup_sourceaddress(struct 
dpu_sw_pipe *pipe,
                return;
 
        if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
-               for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++)
+               for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
                        DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4,
-                                       cfg->layout.plane_addr[i]);
+                                       layout->plane_addr[i]);
        } else if (pipe->multirect_index == DPU_SSPP_RECT_0) {
                DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx,
-                               cfg->layout.plane_addr[0]);
+                               layout->plane_addr[0]);
                DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx,
-                               cfg->layout.plane_addr[2]);
+                               layout->plane_addr[2]);
        } else {
                DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx,
-                               cfg->layout.plane_addr[0]);
+                               layout->plane_addr[0]);
                DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx,
-                               cfg->layout.plane_addr[2]);
+                               layout->plane_addr[2]);
        }
 
        if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
-               ystride0 = (cfg->layout.plane_pitch[0]) |
-                       (cfg->layout.plane_pitch[1] << 16);
-               ystride1 = (cfg->layout.plane_pitch[2]) |
-                       (cfg->layout.plane_pitch[3] << 16);
+               ystride0 = (layout->plane_pitch[0]) |
+                       (layout->plane_pitch[1] << 16);
+               ystride1 = (layout->plane_pitch[2]) |
+                       (layout->plane_pitch[3] << 16);
        } else {
                ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx);
                ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx);
 
                if (pipe->multirect_index == DPU_SSPP_RECT_0) {
                        ystride0 = (ystride0 & 0xFFFF0000) |
-                               (cfg->layout.plane_pitch[0] & 0x0000FFFF);
+                               (layout->plane_pitch[0] & 0x0000FFFF);
                        ystride1 = (ystride1 & 0xFFFF0000)|
-                               (cfg->layout.plane_pitch[2] & 0x0000FFFF);
+                               (layout->plane_pitch[2] & 0x0000FFFF);
                } else {
                        ystride0 = (ystride0 & 0x0000FFFF) |
-                               ((cfg->layout.plane_pitch[0] << 16) &
+                               ((layout->plane_pitch[0] << 16) &
                                 0xFFFF0000);
                        ystride1 = (ystride1 & 0x0000FFFF) |
-                               ((cfg->layout.plane_pitch[2] << 16) &
+                               ((layout->plane_pitch[2] << 16) &
                                 0xFFFF0000);
                }
        }
@@ -564,7 +564,7 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
 static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color)
 {
        struct dpu_hw_sspp *ctx = pipe->sspp;
-       struct dpu_hw_sspp_cfg cfg;
+       struct dpu_hw_fmt_layout cfg;
        u32 idx;
 
        if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index 136b8713943f..100d8e06c90d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -154,13 +154,11 @@ struct dpu_hw_pixel_ext {
 
 /**
  * struct dpu_hw_sspp_cfg : SSPP configuration
- * @layout:    format layout information for programming buffer to hardware
  * @src_rect:  src ROI, caller takes into account the different operations
  *             such as decimation, flip etc to program this field
  * @dest_rect: destination ROI.
  */
 struct dpu_hw_sspp_cfg {
-       struct dpu_hw_fmt_layout layout;
        struct drm_rect src_rect;
        struct drm_rect dst_rect;
 };
@@ -243,10 +241,10 @@ struct dpu_hw_sspp_ops {
        /**
         * setup_sourceaddress - setup pipe source addresses
         * @pipe: Pointer to software pipe context
-        * @cfg: Pointer to pipe config structure
+        * @layout: format layout information for programming buffer to hardware
         */
        void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
-                                   struct dpu_hw_sspp_cfg *cfg);
+                                   struct dpu_hw_fmt_layout *layout);
 
        /**
         * setup_csc - setup color space coversion
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 8c98385303ea..4ae70d21c37a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -471,21 +471,21 @@ static void _dpu_plane_set_qos_remap(struct drm_plane 
*plane)
 
 static void _dpu_plane_set_scanout(struct drm_plane *plane,
                struct dpu_plane_state *pstate,
-               struct dpu_hw_sspp_cfg *pipe_cfg,
                struct drm_framebuffer *fb)
 {
        struct dpu_plane *pdpu = to_dpu_plane(plane);
        struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
        struct msm_gem_address_space *aspace = kms->base.aspace;
+       struct dpu_hw_fmt_layout layout;
        int ret;
 
-       ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
+       ret = dpu_format_populate_layout(aspace, fb, &layout);
        if (ret)
                DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
        else if (pstate->pipe.sspp->ops.setup_sourceaddress) {
                trace_dpu_plane_set_scanout(&pstate->pipe,
-                                           &pipe_cfg->layout);
-               pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, 
pipe_cfg);
+                                           &layout);
+               pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, 
&layout);
        }
 }
 
@@ -1134,7 +1134,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane 
*plane)
 
        memset(&pipe_cfg, 0, sizeof(struct dpu_hw_sspp_cfg));
 
-       _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb);
+       _dpu_plane_set_scanout(plane, pstate, fb);
 
        pstate->pending = true;
 
-- 
2.39.2

Reply via email to