Hi Matt, On Tue, Mar 21, 2023 at 05:10:51PM -0700, Matt Roper wrote: > On Wed, Mar 22, 2023 at 12:20:09AM +0100, Andi Shyti wrote: > > From: Paulo Zanoni <paulo.r.zan...@intel.com> > > > > In multitile systems IRQ need to be reset and enabled per GT. > > At the moment we're not enabling multi-tile support on any platforms > yet. Xe_HP SDV has pretty much already served its purpose as an early > Xe_HP test platform, and most PVC effort is refocusing on the Xe KMD > right now. > > Note that we don't want/need changes like this on non-tile multi-gt > platforms like MTL. The interrupt registers you're accessing here are > sgunit registers so there's only ever a single copy of the register on > such platforms; looping around and processing the same register two > times in a row doesn't accomplish anything that just processing them a > single time doesn't.
Right... irq's registers in MTL are in the root tile. However, In a multi-gt point of view all the "gt" functions need to be iterated over all the GT's... maybe to have things cleaner we might need some dedicated mtl_irq_reset and mtl_irq_postinstall wrappers. Thanks! (again :-)) Andi
