Il 13/04/23 14:46, Guillaume Ranquet ha scritto:
The clock rate calculus in mtk_hdmi_pll_calc() was wrong when it has been replaced by 'div_u64'.Fix the issue by multiplying the values in the denominator instead of dividing them. Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195") Signed-off-by: Guillaume Ranquet <granq...@baylibre.com> --- drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c index e10da6c4147e..5e84b294a43e 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c @@ -271,7 +271,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, * [32,24] 9bit integer, [23,0]:24bit fraction */ pcw = div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH, - da_hdmitx21_ref_ck / PLL_FBKDIV_HS3); + da_hdmitx21_ref_ck * PLL_FBKDIV_HS3);
How did that even work?!?!?!? Because ... it worked, I did test it. Bah! Luck was on your side :-P Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delre...@collabora.com>
