On 17.04.2023 22:21, Marijn Suijten wrote:
> These offsets do not fall under the MDP TOP block and do not fit the
> comment right above. Move them to dpu_hw_interrupts.c next to the
> repsective MDP_INTF_x_OFF interrupt block offsets.
>
> Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
> Signed-off-by: Marijn Suijten <marijn.suij...@somainline.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dyb...@linaro.org>
Konrad
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 5 ++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h | 3 ---
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index 53326f25e40e..85c0bda3ff90 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -15,7 +15,7 @@
>
> /*
> * Register offsets in MDSS register file for the interrupt registers
> - * w.r.t. to the MDP base
> + * w.r.t. the MDP base
> */
> #define MDP_SSPP_TOP0_OFF 0x0
> #define MDP_INTF_0_OFF 0x6A000
> @@ -24,6 +24,9 @@
> #define MDP_INTF_3_OFF 0x6B800
> #define MDP_INTF_4_OFF 0x6C000
> #define MDP_INTF_5_OFF 0x6C800
> +#define INTF_INTR_EN 0x1c0
> +#define INTF_INTR_STATUS 0x1c4
> +#define INTF_INTR_CLEAR 0x1c8
> #define MDP_AD4_0_OFF 0x7C000
> #define MDP_AD4_1_OFF 0x7D000
> #define MDP_AD4_INTR_EN_OFF 0x41c
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
> index feb9a729844a..5acd5683d25a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
> @@ -21,9 +21,6 @@
> #define HIST_INTR_EN 0x01c
> #define HIST_INTR_STATUS 0x020
> #define HIST_INTR_CLEAR 0x024
> -#define INTF_INTR_EN 0x1C0
> -#define INTF_INTR_STATUS 0x1C4
> -#define INTF_INTR_CLEAR 0x1C8
> #define SPLIT_DISPLAY_EN 0x2F4
> #define SPLIT_DISPLAY_UPPER_PIPE_CTRL 0x2F8
> #define DSPP_IGC_COLOR0_RAM_LUTN 0x300
>
