To make way for fractional bpp support, avoid left shifting the
output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.

Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 12 ++++--------
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 +-
 2 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9d5da49f1180..363cfecc1175 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -794,11 +794,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct 
drm_i915_private *i915,
 
        bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, 
pipe_bpp);
 
-       /*
-        * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
-        * fractional part is 0
-        */
-       return bits_per_pixel << 4;
+       return bits_per_pixel;
 }
 
 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
@@ -1188,7 +1184,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
                                                                    
mode->hdisplay,
                                                                    bigjoiner,
                                                                    
output_format,
-                                                                   pipe_bpp, 
64) >> 4;
+                                                                   pipe_bpp, 
64);
                        dsc_slice_count =
                                intel_dp_dsc_get_slice_count(intel_dp,
                                                             target_clock,
@@ -1745,7 +1741,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
                        if (pipe_config->output_format == 
INTEL_OUTPUT_FORMAT_YCBCR420)
                                dsc_max_compressed_bpp = min_t(u16,
                                                               
dsc_max_compressed_bpp,
-                                                              31 << 4);
+                                                              31);
 
                        if (!dsc_max_compressed_bpp) {
                                drm_dbg_kms(&dev_priv->drm,
@@ -1775,7 +1771,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
                                                             
pipe_config->pipe_bpp);
 
                        pipe_config->dsc.compressed_bpp = min_t(u16,
-                                                               
dsc_max_compressed_bpp >> 4,
+                                                               
dsc_max_compressed_bpp,
                                                                output_bpp);
                }
                pipe_config->dsc.slice_count = dsc_dp_slice_count;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index d875fef97356..78821c50948d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -980,7 +980,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
                                                                    
mode->hdisplay,
                                                                    bigjoiner,
                                                                    
INTEL_OUTPUT_FORMAT_RGB,
-                                                                   pipe_bpp, 
64) >> 4;
+                                                                   pipe_bpp, 
64);
                        dsc_slice_count =
                                intel_dp_dsc_get_slice_count(intel_dp,
                                                             target_clock,
-- 
2.25.1

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