On 10/06/2023 01:57, Jessica Zhang wrote:
Add documentation comments explaining the pclk_rate and hdisplay math related to DSC.Signed-off-by: Jessica Zhang <quic_jessz...@quicinc.com> --- drivers/gpu/drm/msm/dsi/dsi_host.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index fb1d3a25765f..aeaadc18bc7b 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -564,6 +564,13 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) static unsigned long dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode, const struct drm_dsc_config *dsc) { + /* + * Adjust the pclk rate by calculating a new hdisplay proportional to + * the compression ratio such that: + * new_hdisplay = old_hdisplay * target_bpp / source_bpp
I'd say `* compressed_bpp / uncompressed_bpp'. This is easier to follow than source and target.
+ * + * Porches need not be adjusted during compression. + */ int new_hdisplay = DIV_ROUND_UP(mode->hdisplay * drm_dsc_get_bpp_int(dsc), dsc->bits_per_component * 3);@@ -961,6 +968,9 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) /* Divide the display by 3 but keep back/font porch and* pulse width same + * + * hdisplay will be divided by 3 here to account for the fact + * that DPU sends 3 bytes per pclk cycle to DSI. */ h_total -= hdisplay; hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 3);
-- With best wishes Dmitry
