The Sitronix datasheet explains BIT(1) of the RGBCTRL register as the DOTCLK/PCLK edge used to sample the data lines:
“0” The data is input on the positive edge of DOTCLK “1” The data is input on the negative edge of DOTCLK IOW, this bit implies a falling edge and not a high state. Correct the definition to ease the comparison with the datasheet. Signed-off-by: Miquel Raynal <miquel.ray...@bootlin.com> --- drivers/gpu/drm/panel/panel-sitronix-st7789v.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7789v.c b/drivers/gpu/drm/panel/panel-sitronix-st7789v.c index 605b9f6d0f14..d7c5b3ad1baa 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7789v.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7789v.c @@ -27,7 +27,7 @@ #define ST7789V_RGBCTRL_RCM(n) (((n) & 3) << 5) #define ST7789V_RGBCTRL_VSYNC_HIGH BIT(3) #define ST7789V_RGBCTRL_HSYNC_HIGH BIT(2) -#define ST7789V_RGBCTRL_PCLK_HIGH BIT(1) +#define ST7789V_RGBCTRL_PCLK_FALLING BIT(1) #define ST7789V_RGBCTRL_DE_LOW BIT(0) #define ST7789V_RGBCTRL_VBP(n) ((n) & 0x7f) #define ST7789V_RGBCTRL_HBP(n) ((n) & 0x1f) @@ -259,7 +259,7 @@ static int st7789v_prepare(struct drm_panel *panel) if (ctx->info->mode->flags & DRM_MODE_FLAG_PHSYNC) polarity |= ST7789V_RGBCTRL_HSYNC_HIGH; if (ctx->info->bus_flags & DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE) - polarity |= ST7789V_RGBCTRL_PCLK_HIGH; + polarity |= ST7789V_RGBCTRL_PCLK_FALLING; if (ctx->info->bus_flags & DRM_BUS_FLAG_DE_LOW) polarity |= ST7789V_RGBCTRL_DE_LOW; -- 2.34.1