On 29.06.2023 14:24, Dmitry Baryshkov wrote: > On Thu, 29 Jun 2023 at 15:14, Marijn Suijten > <marijn.suij...@somainline.org> wrote: >> >> On 2023-06-29 13:56:25, Dmitry Baryshkov wrote: >>> On 27/06/2023 23:14, Marijn Suijten wrote: >>>> Enable and configure the dispcc node on SM6125 for consumption by MDSS >>>> later on. >>>> >>>> Signed-off-by: Marijn Suijten <marijn.suij...@somainline.org> >>>> --- >>>> arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++ >>>> 1 file changed, 25 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>> b/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>> index edb03508dba3..a5cc0d43d2d9 100644 >>>> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>> @@ -3,6 +3,7 @@ >>>> * Copyright (c) 2021, Martin Botka <martin.bo...@somainline.org> >>>> */ >>>> >>>> +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> >>>> #include <dt-bindings/clock/qcom,gcc-sm6125.h> >>>> #include <dt-bindings/clock/qcom,rpmcc.h> >>>> #include <dt-bindings/dma/qcom-gpi.h> >>>> @@ -1203,6 +1204,30 @@ sram@4690000 { >>>> reg = <0x04690000 0x10000>; >>>> }; >>>> >>>> + dispcc: clock-controller@5f00000 { >>>> + compatible = "qcom,sm6125-dispcc"; >>>> + reg = <0x05f00000 0x20000>; >>>> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, >>>> + <0>, >>>> + <0>, >>>> + <0>, >>>> + <0>, >>>> + <0>, >>>> + <&gcc GCC_DISP_AHB_CLK>, >>>> + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; >>>> + clock-names = "bi_tcxo", >>>> + "dsi0_phy_pll_out_byteclk", >>>> + "dsi0_phy_pll_out_dsiclk", >>>> + "dsi1_phy_pll_out_dsiclk", >>>> + "dp_phy_pll_link_clk", >>>> + "dp_phy_pll_vco_div_clk", >>>> + "cfg_ahb_clk", >>>> + "gcc_disp_gpll0_div_clk_src"; >>>> + power-domains = <&rpmpd SM6125_VDDCX>; >>> >>> Would it be logical to specify the required-opps too? >> >> Perhaps, but barely any other SoC aside from sm8x50 sets it on dispcc. >> What should it be, rpmhpd_opp_low_svs? IIRC we used "svs" for the DSI >> PHY despite not having a reference value downstream (it sets a range of >> NOM-TURBO_NO_CPR, and RETENTION when it's off). > > Then for DSI PHY the required-opps should be rpmpd_opp_nom. Yes
> > For the dispcc I think the rpmpd_opp_ret, the lowest possible vote, > should be enough. I'm not 100% sure but not specifying an opp and turning on the domain *******probably******* just sticks with the lowest vote Konrad > >> >> - Marijn >> >>> >>>> + #clock-cells = <1>; >>>> + #power-domain-cells = <1>; >>>> + }; >>>> + >>>> apps_smmu: iommu@c600000 { >>>> compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", >>>> "arm,mmu-500"; >>>> reg = <0x0c600000 0x80000>; >>>> >>> >>> -- >>> With best wishes >>> Dmitry >>> > > >