On 17.07.2023 19:30, Andi Shyti wrote:
Enable the CCS_FLUSH bit 13 in the control pipe for render and compute engines in platforms starting from Meteor Lake (BSPEC 43904 and 47112).Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") Signed-off-by: Andi Shyti <andi.sh...@linux.intel.com> Cc: Jonathan Cavitt <jonathan.cav...@intel.com> Cc: Nirmoy Das <nirmoy....@intel.com> Cc: <sta...@vger.kernel.org> # v5.8+
Reviewed-by: Andrzej Hajda <andrzej.ha...@intel.com> Regards Andrzej
--- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 10 +++++++++- drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 + drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 + 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index 3c935d6b68bf0..aa2fb9d72745a 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -207,7 +207,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) * memory traffic is quiesced prior. */ if ((mode & EMIT_INVALIDATE) && !HAS_FLAT_CCS(engine->i915)) - mode |= EMIT_FLUSH; + mode |= EMIT_FLUSH | EMIT_CCS_FLUSH;if (mode & EMIT_FLUSH) {u32 bit_group_0 = 0; @@ -221,6 +221,14 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH; + /*+ * When required, in MTL+ platforms we need to + * set the CCS_FLUSH bit in the pipe control + */ + if (mode & EMIT_CCS_FLUSH && + GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70)) + bit_group_0 |= PIPE_CONTROL_CCS_FLUSH; + bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH; bit_group_1 |= PIPE_CONTROL_FLUSH_L3; bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index e99a6fa03d453..e2cae9d02bd62 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -514,6 +514,7 @@ struct intel_engine_cs { int (*emit_flush)(struct i915_request *request, u32 mode); #define EMIT_INVALIDATE BIT(0) #define EMIT_FLUSH BIT(1) +#define EMIT_CCS_FLUSH BIT(2) /* MTL+ */ #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH) int (*emit_bb_start)(struct i915_request *rq, u64 offset, u32 length, diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index 5d143e2a8db03..5df7cce23197c 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -299,6 +299,7 @@ #define PIPE_CONTROL_QW_WRITE (1<<14) #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) #define PIPE_CONTROL_DEPTH_STALL (1<<13) +#define PIPE_CONTROL_CCS_FLUSH (1<<13) /* MTL+ */ #define PIPE_CONTROL_WRITE_FLUSH (1<<12) #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on ILK */
