From: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
Now that i915 understands the caching modes behind PAT indices, we can
refine the check in i915_gem_object_can_bypass_llc() to stop assuming any
user PAT can bypass the shared cache (if there is any).
Instead we can use the absence of I915_BO_CACHE_COHERENT_FOR_WRITE as the
criteria, which is set for all caching modes where writes from the CPU
side (in this case buffer clears before handing buffers over to userspace)
are fully coherent with respect to reads from the GPU.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
Cc: Fei Yang <fei.y...@intel.com>
Cc: Matt Roper <matthew.d.ro...@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 18 +++++++++++-------
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index ec1f0be43d0d..8c4b54bd3911 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -221,12 +221,6 @@ bool i915_gem_object_can_bypass_llc(struct
drm_i915_gem_object *obj)
if (!(obj->flags & I915_BO_ALLOC_USER))
return false;
- /*
- * Always flush cache for UMD objects at creation time.
- */
- if (obj->pat_set_by_user)
- return true;
-
/*
* EHL and JSL add the 'Bypass LLC' MOCS entry, which should make it
* possible for userspace to bypass the GTT caching bits set by the
@@ -239,7 +233,17 @@ bool i915_gem_object_can_bypass_llc(struct
drm_i915_gem_object *obj)
* it, but since i915 takes the stance of always zeroing memory before
* handing it to userspace, we need to prevent this.
*/
- return IS_JSL_EHL(i915);
+ if (IS_JSL_EHL(i915))
+ return true;
+
+ /*
+ * Any caching mode where writes via CPU cache are not coherent with
+ * the GPU needs explicit flushing to ensure GPU can not see stale data.
+ */
+ if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE))
+ return true;
+
+ return false;
}
static void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file
*file)
--
2.39.2
