[PATCH 3/3] drm/sun4i: tcon: parent keeps TCON0 clock stable on A64

[Frank Oltmanns]

From: Icenowy Zheng <icen...@aosc.io>

As the clk framework keeps A64's TCON0 clock stable when HDMI changes
its parent's clock, do not protect TCON0 clock on A64 in the TCON driver
to allow PLL-Video0 to get changed by HDMI.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Signed-off-by: Frank Oltmanns <fr...@oltmanns.dev>
---
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 15 +++++++++++++--
 drivers/gpu/drm/sun4i/sun4i_tcon.h |  1 +
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c 
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 6a52fb12cbfb..4439e62b7a34 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -108,9 +108,11 @@ static void sun4i_tcon_channel_set_status(struct 
sun4i_tcon *tcon, int channel,
 
        if (enabled) {
                clk_prepare_enable(clk);
-               clk_rate_exclusive_get(clk);
+               if (!tcon->quirks->rate_kept_by_parent)
+                       clk_rate_exclusive_get(clk);
        } else {
-               clk_rate_exclusive_put(clk);
+               if (!tcon->quirks->rate_kept_by_parent)
+                       clk_rate_exclusive_put(clk);
                clk_disable_unprepare(clk);
        }
 }
@@ -1505,6 +1507,14 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = 
{
        .supports_lvds          = true,
 };
 
+static const struct sun4i_tcon_quirks sun50i_a64_lcd_quirks = {
+       .supports_lvds          = true,
+       .has_channel_0          = true,
+       .rate_kept_by_parent    = true,
+       .dclk_min_div           = 1,
+       .setup_lvds_phy         = sun6i_tcon_setup_lvds_phy,
+};
+
 static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
        .supports_lvds          = true,
        .has_channel_0          = true,
@@ -1563,6 +1573,7 @@ const struct of_device_id sun4i_tcon_of_table[] = {
        { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = 
&sun9i_a80_tcon_tv_quirks },
        { .compatible = "allwinner,sun20i-d1-tcon-lcd", .data = 
&sun20i_d1_lcd_quirks },
        { .compatible = "allwinner,sun20i-d1-tcon-tv", .data = 
&sun8i_r40_tv_quirks },
+       { .compatible = "allwinner,sun50i-a64-tcon-lcd", .data = 
&sun50i_a64_lcd_quirks },
        { }
 };
 MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h 
b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index fa23aa23fe4a..c4ce7c29192e 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -243,6 +243,7 @@ struct sun4i_tcon_quirks {
        bool    needs_edp_reset; /* a80 edp reset needed for tcon0 access */
        bool    supports_lvds;   /* Does the TCON support an LVDS output? */
        bool    polarity_in_ch0; /* some tcon1 channels have polarity bits in 
tcon0 pol register */
+       bool    rate_kept_by_parent; /* Does parent keep TCON0 clock stable? */
        u8      dclk_min_div;   /* minimum divider for TCON0 DCLK */
 
        /* callback to handle tcon muxing options */

-- 
2.41.0