Connecting a 320x240 parallel display on i.MX6 resulted in an invalid DRDY
signal because the DC would not receive NL/EOL events on every line.
Reducing the allocated DMFC space from 4 slots (256 * 128-bit) to 2 slots
(128 * 128-bit) solved the problem.
Signed-off-by: Philipp Zabel <p.za...@pengutronix.de>
---
drivers/staging/imx-drm/ipu-v3/ipu-dmfc.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-dmfc.c
b/drivers/staging/imx-drm/ipu-v3/ipu-dmfc.c
index 2e97c33..98070dd 100644
--- a/drivers/staging/imx-drm/ipu-v3/ipu-dmfc.c
+++ b/drivers/staging/imx-drm/ipu-v3/ipu-dmfc.c
@@ -307,13 +307,13 @@ int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
goto out;
}
- /* Always allocate at least 128*4 bytes (2 slots) */
- if (slots < 2)
- slots = 2;
-
/* For the MEM_BG channel, first try to allocate twice the slots */
if (dmfc->data->ipu_channel == IPUV3_CHANNEL_MEM_BG_SYNC)
segment = dmfc_find_slots(priv, slots * 2);
+ else if (slots < 2)
+ /* Always allocate at least 128*4 bytes (2 slots) */
+ slots = 2;
+
if (segment >= 0)
slots *= 2;
else
--
1.8.4.rc3
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