On Wed, Nov 22, 2023 at 12:30:03PM -0800, Alan Previn wrote:
> Add missing tag for "Wa_14019159160 - Case 2" (for existing
> PXP code that ensures run alone mode bit is set to allow
> PxP-decryption.
>
> v2: - Fix WA id number (John Harrison).
> - Improve comments and code to be specific
> for the targetted platforms (John Harrison)
>
> Signed-off-by: Alan Previn <alan.previn.teres.ale...@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 7c367ba8d9dc..2959dfed2aa0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -863,11 +863,13 @@ static bool ctx_needs_runalone(const struct
> intel_context *ce)
> bool ctx_is_protected = false;
>
> /*
> - * On MTL and newer platforms, protected contexts require setting
> - * the LRC run-alone bit or else the encryption will not happen.
> + * Wa_14019159160 - Case 2: mtl
> + * On some platforms, protected contexts require setting
> + * the LRC run-alone bit or else the encryption/decryption will not
> happen.
> + * NOTE: Case 2 only applies to PXP use-case of said workaround.
> */
hmm, interesting enough, on the wa description I read that it is incomplete for
MTL/ARL
and something about a fuse bit. We should probably chase for some clarification
in the
HSD?!
> - if (GRAPHICS_VER_FULL(ce->engine->i915) >= IP_VER(12, 70) &&
> - (ce->engine->class == COMPUTE_CLASS || ce->engine->class ==
> RENDER_CLASS)) {
> + if (IS_METEORLAKE(ce->engine->i915) && (ce->engine->class ==
> COMPUTE_CLASS ||
> + ce->engine->class ==
> RENDER_CLASS)) {
This check now excludes the ARL with the same IP, no?!
> rcu_read_lock();
> gem_ctx = rcu_dereference(ce->gem_context);
> if (gem_ctx)
>
> base-commit: 5429d55de723544dfc0630cf39d96392052b27a1
> --
> 2.39.0
>
