With a value of '0' read from MSTM_CAP register MST to be enabled.
DP2.1 SCR updates the spec for 128/132b DP capable supporting only one
stream and not supporting single stream sideband MSG.
The underlying protocol will be MST to enable use of MTP.
Signed-off-by: Arun R Murthy <arun.r.mur...@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9ff0cbd9c0df..05722f10cdd7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4037,9 +4037,15 @@ intel_dp_configure_mst(struct intel_dp *intel_dp)
if (!intel_dp_mst_source_support(intel_dp))
return;
-
- intel_dp->is_mst = sink_can_mst &&
- i915->display.params.enable_dp_mst;
+ /*
+ * Even if dpcd reg MSTM_CAP is 0, if the sink supports UHBR rates then
+ * DP2.1 can be enabled with underlying protocol using MST for MTP
+ * TODO: Need to accommodate MSTM_CAP bit[0]=0, bit[1]=1 condition, i.e
+ * one stream with single stream sideband msg.
+ */
+ intel_dp->is_mst = (sink_can_mst ||
(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] &
+ DP_CAP_ANSI_128B132B)) &&
+ i915->display.params.enable_dp_mst;
drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
intel_dp->is_mst);
--
2.25.1
