On 2/22/2024 1:46 AM, Dmitry Baryshkov wrote:
On Thu, 22 Feb 2024 at 11:28, Konrad Dybcio <konrad.dyb...@linaro.org> wrote:
On 2/22/24 10:04, Dmitry Baryshkov wrote:
On Thu, 22 Feb 2024 at 10:56, Konrad Dybcio <konrad.dyb...@linaro.org> wrote:
On 2/22/24 00:41, Dmitry Baryshkov wrote:
On Thu, 22 Feb 2024 at 01:19, Bjorn Andersson <quic_bjora...@quicinc.com> wrote:
The max frequency listed in the DPU opp-table is 506MHz, this is not
sufficient to drive a 4k@60 display, resulting in constant underrun.
Add the missing MDP_CLK turbo frequency of 608MHz to the opp-table to
fix this.
I think we might want to keep this disabled for ChromeOS devices. Doug?
ChromeOS devices don't get a special SoC
But they have the sc7280-chrome-common.dtsi, which might contain a
corresponding /delete-node/ .
What does that change? The clock rates are bound to the
SoC and the effective values are limited by link-frequencies
or the panel driver.
Preventing the DPU from overheating? Or spending too much power?
Running DPU clock in turbo is a requirement to support 4k@60 otherwise
the pixel rate that high cannot be supported.
sc7280 chrome devices already limit to HBR2
https://lore.kernel.org/all/20230329233416.27152-1-quic_abhin...@quicinc.com/
So the DPU will not vote more than nominal.
And like others wrote, limiting SOC frequencies is not the way and we
should filter out required frequencies using link-frequencies.
Hence fwiw, I am fine with this change.
Reviewed-by: Abhinav Kumar <quic_abhin...@quicinc.com>
