On 2/23/2024 1:21 PM, Konrad Dybcio wrote: > + /* Wait 50us for PLL_LOCK_DET bit to go high */ > + usleep_range(50, 55); > + > + /* Enable PLL output */ > + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); > +} > +EXPORT_SYMBOL(clk_huayra_2290_pll_configure);
Please use EXPORT_SYMBOL_GPL. -- ---Trilok Soni
