Add the speedbin masks to ensure only the desired OPPs are available on
chips of a given bin.

Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz.

Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dyb...@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi 
b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 4c9820adcf52..c1e3cec1540a 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2119,48 +2119,67 @@ zap-shader {
                                memory-region = <&gpu_micro_code_mem>;
                        };
 
-                       /* Speedbin needs more work on A740+, keep only lower 
freqs */
                        gpu_opp_table: opp-table {
                                compatible = "operating-points-v2";
 
+                               opp-719000000 {
+                                       opp-hz = /bits/ 64 <719000000>;
+                                       opp-level = 
<RPMH_REGULATOR_LEVEL_SVS_L2>;
+                                       opp-supported-hw = <0x1>;
+                               };
+
                                opp-680000000 {
                                        opp-hz = /bits/ 64 <680000000>;
                                        opp-level = 
<RPMH_REGULATOR_LEVEL_SVS_L1>;
+                                       opp-supported-hw = <0x3>;
                                };
 
                                opp-615000000 {
                                        opp-hz = /bits/ 64 <615000000>;
                                        opp-level = 
<RPMH_REGULATOR_LEVEL_SVS_L0>;
+                                       opp-supported-hw = <0x3>;
                                };
 
                                opp-550000000 {
                                        opp-hz = /bits/ 64 <550000000>;
                                        opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+                                       opp-supported-hw = <0x3>;
                                };
 
                                opp-475000000 {
                                        opp-hz = /bits/ 64 <475000000>;
                                        opp-level = 
<RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+                                       opp-supported-hw = <0x3>;
                                };
 
                                opp-401000000 {
                                        opp-hz = /bits/ 64 <401000000>;
                                        opp-level = 
<RPMH_REGULATOR_LEVEL_LOW_SVS>;
+                                       opp-supported-hw = <0x3>;
                                };
 
                                opp-348000000 {
                                        opp-hz = /bits/ 64 <348000000>;
                                        opp-level = 
<RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+                                       opp-supported-hw = <0x3>;
                                };
 
                                opp-295000000 {
                                        opp-hz = /bits/ 64 <295000000>;
                                        opp-level = 
<RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+                                       opp-supported-hw = <0x3>;
                                };
 
                                opp-220000000 {
                                        opp-hz = /bits/ 64 <220000000>;
                                        opp-level = 
<RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+                                       opp-supported-hw = <0x3>;
+                               };
+
+                               opp-124800000 {
+                                       opp-hz = /bits/ 64 <124800000>;
+                                       opp-level = 
<RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+                                       opp-supported-hw = <0x3>;
                                };
                        };
                };

-- 
2.45.2

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