Replace the BPP_X16_FMT()/ARGS() helpers defined by the driver with the
equivalent FXP_Q4_FMT()/ARGS() helpers defined by DRM core.
v2: Rebase on the s/DRM_X16/FXP_Q4 change.
Signed-off-by: Imre Deak <imre.d...@intel.com>
---
drivers/gpu/drm/i915/display/intel_audio.c | 5 +++--
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
.../gpu/drm/i915/display/intel_display_types.h | 3 ---
drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++--------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++--
5 files changed, 15 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index b9bafec06fb8b..9b8508a503f7f 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -26,6 +26,7 @@
#include <drm/drm_edid.h>
#include <drm/drm_eld.h>
+#include <drm/drm_fixed.h>
#include <drm/intel/i915_component.h>
#include "i915_drv.h"
@@ -452,8 +453,8 @@ static unsigned int calc_hblank_early_prog(struct
intel_encoder *encoder,
lanes = crtc_state->lane_count;
drm_dbg_kms(&i915->drm,
- "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = "
BPP_X16_FMT " cdclk = %u\n",
- h_active, link_clk, lanes, BPP_X16_ARGS(vdsc_bppx16),
cdclk);
+ "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = "
FXP_Q4_FMT " cdclk = %u\n",
+ h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk);
if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 ||
!cdclk))
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 49628dd891883..17dba8aa16694 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4672,9 +4672,9 @@ intel_modeset_pipe_config(struct intel_atomic_state
*state,
if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16))
{
drm_dbg_kms(&i915->drm,
- "[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT
"\n",
+ "[CRTC:%d:%s] Link bpp limited to " FXP_Q4_FMT "\n",
crtc->base.base.id, crtc->base.name,
- BPP_X16_ARGS(crtc_state->max_link_bpp_x16));
+ FXP_Q4_ARGS(crtc_state->max_link_bpp_x16));
crtc_state->bw_constrained = true;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index e8b42ceed9529..38a0eff249fa8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2178,9 +2178,6 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
-#define BPP_X16_FMT "%d.%04d"
-#define BPP_X16_ARGS(bpp_x16) fxp_q4_to_int(bpp_x16),
(fxp_q4_to_frac(bpp_x16) * 625)
-
/*
* Conversion functions/macros from various pointer types to struct
* intel_display pointer.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 4c078ff664005..6a77655dee453 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2271,17 +2271,17 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
if (ret < 0) {
drm_dbg_kms(&dev_priv->drm,
"Cannot compute valid DSC parameters for Input Bpp
= %d"
- "Compressed BPP = " BPP_X16_FMT "\n",
+ "Compressed BPP = " FXP_Q4_FMT "\n",
pipe_config->pipe_bpp,
- BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
+ FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16));
return ret;
}
pipe_config->dsc.compression_enable = true;
drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
- "Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n",
+ "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n",
pipe_config->pipe_bpp,
- BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
+ FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
pipe_config->dsc.slice_count);
return 0;
@@ -2334,7 +2334,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp
*intel_dp,
limits->link.max_bpp_x16 = max_link_bpp_x16;
drm_dbg_kms(&i915->drm,
- "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d
kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT
"\n",
+ "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d
kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT
"\n",
encoder->base.base.id, encoder->base.name,
crtc->base.base.id, crtc->base.name,
adjusted_mode->crtc_clock,
@@ -2342,7 +2342,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp
*intel_dp,
limits->max_lane_count,
limits->max_rate,
limits->pipe.max_bpp,
- BPP_X16_ARGS(limits->link.max_bpp_x16));
+ FXP_Q4_ARGS(limits->link.max_bpp_x16));
return true;
}
@@ -2473,10 +2473,10 @@ intel_dp_compute_link_config(struct intel_encoder
*encoder,
}
drm_dbg_kms(&i915->drm,
- "DP lane count %d clock %d bpp input %d compressed "
BPP_X16_FMT " link rate required %d available %d\n",
+ "DP lane count %d clock %d bpp input %d compressed "
FXP_Q4_FMT " link rate required %d available %d\n",
pipe_config->lane_count, pipe_config->port_clock,
pipe_config->pipe_bpp,
- BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
+ FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
intel_dp_config_required_rate(pipe_config),
intel_dp_max_link_data_rate(intel_dp,
pipe_config->port_clock,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3f863ddb0c597..eda743866e7f7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -497,10 +497,10 @@ adjust_limits_for_dsc_hblank_expansion_quirk(const struct
intel_connector *conne
return true;
drm_dbg_kms(&i915->drm,
- "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to "
BPP_X16_FMT " in DSC mode due to hblank expansion quirk\n",
+ "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to "
FXP_Q4_FMT " in DSC mode due to hblank expansion quirk\n",
crtc->base.base.id, crtc->base.name,
connector->base.base.id, connector->base.name,
- BPP_X16_ARGS(min_bpp_x16));
+ FXP_Q4_ARGS(min_bpp_x16));
if (limits->link.max_bpp_x16 < min_bpp_x16)
return false;
--
2.43.3
