[PATCH 4/5] drm/msm/a6xx: Set GMU CGC properties on a6xx too

[Konrad Dybcio]

This was apparently never done before.. Program the expected values.

Signed-off-by: Konrad Dybcio <konrad.dyb...@linaro.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 18 ++++++++++--------
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  8 +++++++-
 2 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 871452daa189..33a319f7d200 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -402,6 +402,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
        struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
        const struct adreno_reglist *reg;
        unsigned int i;
+       u32 cgc_delay, cgc_hyst;
        u32 val, clock_cntl_on;
 
        if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu)))
@@ -416,14 +417,15 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
        else
                clock_cntl_on = 0x8aa8aa82;
 
-       if (adreno_is_a7xx(adreno_gpu)) {
-               gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
-                         state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
-               gmu_write(&a6xx_gpu->gmu, 
REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
-                         state ? 0x10111 : 0);
-               gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,
-                         state ? 0x5555 : 0);
-       }
+       cgc_delay = adreno_is_a615_family(adreno_gpu) ? 0x111 : 0x10111;
+       cgc_hyst = adreno_is_a615_family(adreno_gpu) ? 0x555 : 0x5555;
+
+       gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
+                       state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
+       gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
+                       state ? cgc_delay : 0);
+       gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,
+                       state ? cgc_hyst : 0);
 
        if (!adreno_gpu->info->a6xx->hwcg) {
                gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 1ab523a163a0..26972b2cc896 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -433,7 +433,13 @@ static inline int adreno_is_a610_family(const struct 
adreno_gpu *gpu)
        return adreno_is_a610(gpu) || adreno_is_a702(gpu);
 }
 
-/* check for a615, a616, a618, a619 or any a630 derivatives */
+/* TODO: 615/616 */
+static inline int adreno_is_a615_family(const struct adreno_gpu *gpu)
+{
+       return adreno_is_a618(gpu) ||
+              adreno_is_a619(gpu);
+}
+
 static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
 {
        if (WARN_ON_ONCE(!gpu->info))

-- 
2.45.2