Hi Heiko,
At 2025-02-12 18:59:50, "Heiko Stübner" <[email protected]> wrote:
>Hi Andy,
>
>Am Mittwoch, 12. Februar 2025, 10:34:57 MEZ schrieb Andy Yan:
>> From: Andy Yan <[email protected]>
>>
>> This help avoid "exceeds 100 columns" warning from checkpatch
>>
>> Signed-off-by: Andy Yan <[email protected]>
>
>I'm not much of a fan of "randomly" renaming individual constants
>(especially when one is now named OFFS, while the rest stay at OFFSET)
>
>- on rk3568 VOP2_CLUSTER_WIN0_TRANSFORMED_OFFSET = WIN0 transformed offset
>- on rk3588 VOP2_CLUSTER0_WIN0_TRANSFORMED_OFFSET = WIN0 transform offset
>- on rk3576 "someone" sadly decided to not provide the 2nd TRM part anymore
> but I guess it'll be the same.
>
>So instead of just dropping parts from the end, you could also follow
>the TRM naming and drop the "_AFBC" from the register name instead?
>
>So going to VOP2_WIN_TRANSFORM_OFFSET, this would also reduce the line
>length accordingly, and moving the naming closer to the TRM too.
I choose to drop the AFBC prefix. As this register needs to be configured not
only
in AFBC mode, but also in tile mode.
And I don't particularly like use linebreak.
>
>Alternatively, just add a linebreak at the appropriate position instead.
>
>Heiko
>
>
>> ---
>>
>> (no changes since v1)
>>
>> drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 8 ++++----
>> drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 4 ++--
>> 2 files changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
>> b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
>> index ebc9cb93073c..8e1b742a7550 100644
>> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
>> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
>> @@ -1524,7 +1524,7 @@ static void vop2_plane_atomic_update(struct drm_plane
>> *plane,
>> transform_offset = vop2_afbc_transform_offset(pstate,
>> half_block_en);
>> vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst);
>> vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info);
>> - vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET,
>> transform_offset);
>> + vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFS,
>> transform_offset);
>> vop2_win_write(win, VOP2_WIN_AFBC_PIC_OFFSET, ((src->x1 >> 16)
>> | src->y1));
>> vop2_win_write(win, VOP2_WIN_AFBC_DSP_OFFSET, (dest->x1 |
>> (dest->y1 << 16)));
>> vop2_win_write(win, VOP2_WIN_AFBC_PIC_VIR_WIDTH, stride);
>> @@ -1535,7 +1535,7 @@ static void vop2_plane_atomic_update(struct drm_plane
>> *plane,
>> } else {
>> if (vop2_cluster_window(win)) {
>> vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 0);
>> - vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, 0);
>> + vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFS, 0);
>> }
>>
>> vop2_win_write(win, VOP2_WIN_YRGB_VIR,
>> DIV_ROUND_UP(fb->pitches[0], 4));
>> @@ -3448,7 +3448,7 @@ static const struct reg_field
>> vop2_cluster_regs[VOP2_WIN_MAX_REG] = {
>> [VOP2_WIN_AFBC_TILE_NUM] =
>> REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 16, 31),
>> [VOP2_WIN_AFBC_PIC_OFFSET] =
>> REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET, 0, 31),
>> [VOP2_WIN_AFBC_DSP_OFFSET] =
>> REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET, 0, 31),
>> - [VOP2_WIN_AFBC_TRANSFORM_OFFSET] =
>> REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET, 0, 31),
>> + [VOP2_WIN_AFBC_TRANSFORM_OFFS] =
>> REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFS, 0, 31),
>> [VOP2_WIN_AFBC_ROTATE_90] =
>> REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 0, 0),
>> [VOP2_WIN_AFBC_ROTATE_270] =
>> REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 1, 1),
>> [VOP2_WIN_XMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2,
>> 2),
>> @@ -3547,7 +3547,7 @@ static const struct reg_field
>> vop2_esmart_regs[VOP2_WIN_MAX_REG] = {
>> [VOP2_WIN_AFBC_PIC_OFFSET] = { .reg = 0xffffffff },
>> [VOP2_WIN_AFBC_PIC_SIZE] = { .reg = 0xffffffff },
>> [VOP2_WIN_AFBC_DSP_OFFSET] = { .reg = 0xffffffff },
>> - [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = { .reg = 0xffffffff },
>> + [VOP2_WIN_AFBC_TRANSFORM_OFFS] = { .reg = 0xffffffff },
>> [VOP2_WIN_AFBC_HDR_PTR] = { .reg = 0xffffffff },
>> [VOP2_WIN_AFBC_HALF_BLOCK_EN] = { .reg = 0xffffffff },
>> [VOP2_WIN_AFBC_ROTATE_270] = { .reg = 0xffffffff },
>> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
>> b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
>> index 29cc7fb8f6d8..8510140b0869 100644
>> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
>> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
>> @@ -118,7 +118,7 @@ enum vop2_win_regs {
>> VOP2_WIN_AFBC_PIC_OFFSET,
>> VOP2_WIN_AFBC_PIC_SIZE,
>> VOP2_WIN_AFBC_DSP_OFFSET,
>> - VOP2_WIN_AFBC_TRANSFORM_OFFSET,
>> + VOP2_WIN_AFBC_TRANSFORM_OFFS,
>> VOP2_WIN_AFBC_HDR_PTR,
>> VOP2_WIN_AFBC_HALF_BLOCK_EN,
>> VOP2_WIN_AFBC_ROTATE_270,
>> @@ -335,7 +335,7 @@ enum dst_factor_mode {
>> #define RK3568_CLUSTER_WIN_DSP_INFO 0x24
>> #define RK3568_CLUSTER_WIN_DSP_ST 0x28
>> #define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB 0x30
>> -#define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET 0x3C
>> +#define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFS 0x3C
>> #define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL 0x50
>> #define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE 0x54
>> #define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR 0x58
>>
>
>
>
>
>
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