On Sat,  6 Aug 2011 10:54:05 -0700
Keith Packard <keithp at keithp.com> wrote:

> During mode setting, check to make sure the panel power sequencing has
> completed before doing further operations on the device. This
> uncovered errors with DPMS not turning the device off as it was left locked.
> 
> Signed-off-by: Keith Packard <keithp at keithp.com>
> ---
>  drivers/gpu/drm/i915/intel_lvds.c |   13 +++++++++++--
>  1 files changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c 
> b/drivers/gpu/drm/i915/intel_lvds.c
> index 2e8ddfc..6985e42 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -72,14 +72,16 @@ static void intel_lvds_enable(struct intel_lvds 
> *intel_lvds)
>  {
>       struct drm_device *dev = intel_lvds->base.base.dev;
>       struct drm_i915_private *dev_priv = dev->dev_private;
> -     u32 ctl_reg, lvds_reg;
> +     u32 ctl_reg, lvds_reg, stat_reg;
>  
>       if (HAS_PCH_SPLIT(dev)) {
>               ctl_reg = PCH_PP_CONTROL;
>               lvds_reg = PCH_LVDS;
> +             stat_reg = PCH_PP_STATUS;
>       } else {
>               ctl_reg = PP_CONTROL;
>               lvds_reg = LVDS;
> +             stat_reg = PP_STATUS;
>       }
>  
>       I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
> @@ -105,6 +107,8 @@ static void intel_lvds_enable(struct intel_lvds 
> *intel_lvds)
>  
>       I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
>       POSTING_READ(lvds_reg);
> +     if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
> +             DRM_ERROR("timed out waiting for panel to power on\n");

Looks like maybe we want a small function for this...

>       I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
> +     if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
> +             DRM_ERROR("timed out waiting for panel to power off status 
> 0x%08x control 0x%08x\n",
> +                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));

...to catch places like this where the wrong register gets used. :)


-- 
Jesse Barnes, Intel Open Source Technology Center

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