[PATCH v2 01/13] drm/bridge: samsung-dsim: separate LINK and DPHY status registers

[Kaustabh Chakraborty]

Exynos7870's DSIM has separate registers for LINK and DPHY status. This
is in contrast to other devices in the driver which use a single
register for both.

Add their respective entries in the register list. Devices having a
single status register have been assigned the same offset for both
entries.

Signed-off-by: Kaustabh Chakraborty <kauschl...@disroot.org>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c 
b/drivers/gpu/drm/bridge/samsung-dsim.c
index 
f2f666b27d2d5ec016d7a7f47c87fcdf1377d41a..7fd4c34cdc3170d363942f98feec048097da3c06
 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -30,7 +30,7 @@
 /* returns true iff both arguments logically differs */
 #define NEQV(a, b) (!(a) ^ !(b))
 
-/* DSIM_STATUS */
+/* DSIM_DPHY_STATUS */
 #define DSIM_STOP_STATE_DAT(x)         (((x) & 0xf) << 0)
 #define DSIM_STOP_STATE_CLK            BIT(8)
 #define DSIM_TX_READY_HS_CLK           BIT(10)
@@ -239,7 +239,8 @@ enum samsung_dsim_transfer_type {
 };
 
 enum reg_idx {
-       DSIM_STATUS_REG,        /* Status register */
+       DSIM_LINK_STATUS_REG,   /* Link status register */
+       DSIM_DPHY_STATUS_REG,   /* D-PHY status register */
        DSIM_SWRST_REG,         /* Software reset register */
        DSIM_CLKCTRL_REG,       /* Clock control register */
        DSIM_TIMEOUT_REG,       /* Time out register */
@@ -264,7 +265,8 @@ enum reg_idx {
 };
 
 static const unsigned int exynos_reg_ofs[] = {
-       [DSIM_STATUS_REG] =  0x00,
+       [DSIM_LINK_STATUS_REG] =  0x00,
+       [DSIM_DPHY_STATUS_REG] =  0x00,
        [DSIM_SWRST_REG] =  0x04,
        [DSIM_CLKCTRL_REG] =  0x08,
        [DSIM_TIMEOUT_REG] =  0x0c,
@@ -288,7 +290,8 @@ static const unsigned int exynos_reg_ofs[] = {
 };
 
 static const unsigned int exynos5433_reg_ofs[] = {
-       [DSIM_STATUS_REG] = 0x04,
+       [DSIM_LINK_STATUS_REG] = 0x04,
+       [DSIM_DPHY_STATUS_REG] = 0x04,
        [DSIM_SWRST_REG] = 0x0C,
        [DSIM_CLKCTRL_REG] = 0x10,
        [DSIM_TIMEOUT_REG] = 0x14,
@@ -690,7 +693,7 @@ static unsigned long samsung_dsim_set_pll(struct 
samsung_dsim *dsi,
                        dev_err(dsi->dev, "PLL failed to stabilize\n");
                        return 0;
                }
-               reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
+               reg = samsung_dsim_read(dsi, DSIM_LINK_STATUS_REG);
        } while ((reg & DSIM_PLL_STABLE) == 0);
 
        dsi->hs_clock = fout;
@@ -966,7 +969,7 @@ static int samsung_dsim_init_link(struct samsung_dsim *dsi)
                        return -EFAULT;
                }
 
-               reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
+               reg = samsung_dsim_read(dsi, DSIM_DPHY_STATUS_REG);
                if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
                    != DSIM_STOP_STATE_DAT(lanes_mask))
                        continue;

-- 
2.49.0