On Thu, 12 Jun 2025 00:47:46 +0300, Cristian Ciocaltea wrote:
> Since commit c871a311edf0 ("phy: rockchip: samsung-hdptx: Setup TMDS
> char rate via phy_configure_opts_hdmi"), the workaround of passing the
> PHY rate from DW HDMI QP bridge driver via phy_set_bus_width() became
> partially broken, unless the rate adjustment is done as with RK3588,
> i.e. by CCF from VOP2.
>
> Attempting to fix this up at PHY level would not only introduce
> additional hacks, but it would also fail to adequately resolve the
> display issues that are a consequence of the system CRU limitations.
>
> [...]
Applied, thanks!
[1/3] dt-bindings: display: vop2: Add optional PLL clock property for rk3576
commit: 3832dc42aed9b047ccecebf5917d008bd2dac940
Best regards,
--
Heiko Stuebner <he...@sntech.de>
