[PATCH 09/12] drm: sprd: add support for newer DPU versions

[Otto Pflüger]

Newer DPU revisions such as the one used in UMS9230 (version 5) do not
have internal MMU registers and also require different defaults for the
display interface configuration.

Check the DPU version register to account for these configuration
differences.

Signed-off-by: Otto Pflüger <otto.pflue...@abscue.de>
---
 drivers/gpu/drm/sprd/sprd_dpu.c | 30 ++++++++++++++++++++----------
 1 file changed, 20 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/sprd/sprd_dpu.c b/drivers/gpu/drm/sprd/sprd_dpu.c
index 
575bcdb0e0bb30055ac5c3d0e65178cc9f6611f3..01906243a93e3306fbce5bf617838b517822a2b6
 100644
--- a/drivers/gpu/drm/sprd/sprd_dpu.c
+++ b/drivers/gpu/drm/sprd/sprd_dpu.c
@@ -27,6 +27,7 @@
 #include "sprd_dsi.h"
 
 /* Global control registers */
+#define REG_DPU_VERSION        0x00
 #define REG_DPU_CTRL   0x04
 #define REG_DPU_CFG0   0x08
 #define REG_PANEL_SIZE 0x20
@@ -406,22 +407,31 @@ static void sprd_dpu_init(struct sprd_dpu *dpu)
 {
        struct dpu_context *ctx = &dpu->ctx;
        u32 int_mask = 0;
+       u32 dpu_version = readl(ctx->base + REG_DPU_VERSION);
 
        writel(0x00, ctx->base + REG_BG_COLOR);
-       writel(0x00, ctx->base + REG_MMU_EN);
-       writel(0x00, ctx->base + REG_MMU_PPN1);
-       writel(0xffff, ctx->base + REG_MMU_RANGE1);
-       writel(0x00, ctx->base + REG_MMU_PPN2);
-       writel(0xffff, ctx->base + REG_MMU_RANGE2);
-       writel(0x1ffff, ctx->base + REG_MMU_VPN_RANGE);
+       if (dpu_version < 0x300) {
+               writel(0x00, ctx->base + REG_MMU_EN);
+               writel(0x00, ctx->base + REG_MMU_PPN1);
+               writel(0xffff, ctx->base + REG_MMU_RANGE1);
+               writel(0x00, ctx->base + REG_MMU_PPN2);
+               writel(0xffff, ctx->base + REG_MMU_RANGE2);
+               writel(0x1ffff, ctx->base + REG_MMU_VPN_RANGE);
+       }
 
        if (ctx->if_type == SPRD_DPU_IF_DPI) {
                /* use dpi as interface */
                dpu_reg_clr(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
-               /* disable Halt function for SPRD DSI */
-               dpu_reg_clr(ctx, REG_DPI_CTRL, BIT_DPU_DPI_HALT_EN);
-               /* select te from external pad */
-               dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
+
+               if (dpu_version < 0x300) {
+                       /* disable Halt function for SPRD DSI */
+                       dpu_reg_clr(ctx, REG_DPI_CTRL, BIT_DPU_DPI_HALT_EN);
+                       /* select te from external pad */
+                       dpu_reg_set(ctx, REG_DPI_CTRL, 
BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
+               } else {
+                       /* enable Halt function for SPRD DSI */
+                       dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_DPI_HALT_EN);
+               }
 
                /* enable dpu update done INT */
                int_mask |= BIT_DPU_INT_UPDATE_DONE;

-- 
2.50.0