On 7/22/2025 8:25 PM, Konrad Dybcio wrote:
> On 7/20/25 2:16 PM, Akhil P Oommen wrote:
>> Add the IFPC restore register list and enable IFPC support on Adreno
>> X1-85 gpu.
>>
>> Signed-off-by: Akhil P Oommen <akhi...@oss.qualcomm.com>
>> ---
>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 67
>> ++++++++++++++++++++++++++++++-
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++++--
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
>> 3 files changed, 78 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> index
>> 70f7ad806c34076352d84f32d62c2833422b6e5e..07fcabed472c3b9ca47faf1a8b3f7cf580801981
>> 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> @@ -1343,6 +1343,69 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = {
>>
>> DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist);
>>
>> +/* Applicable for X185, A750 */
>> +static const u32 a750_ifpc_reglist_regs[] = {
>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0,
>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
>> + REG_A6XX_TPL1_NC_MODE_CNTL,
>> + REG_A6XX_SP_NC_MODE_CNTL,
>> + REG_A6XX_CP_DBG_ECO_CNTL,
>> + REG_A6XX_CP_PROTECT_CNTL,
>> + REG_A6XX_CP_PROTECT(0),
>> + REG_A6XX_CP_PROTECT(1),
>
> Is it fair to assume that we'd like to saverestore all CP_PROT
> registers on all SKUs, always? We can save some space in .rodata
> this way..
Yeah. Makes sense, but lets do that when we duplicate it in future.
-Akhil
>
> Konrad
