On Wed, Jul 16, 2025 at 06:04:29PM +0800, Andy Yan wrote:
> From: Andy Yan <andy....@rock-chips.com>
>
> The DW DP TX Controller is compliant with the DisplayPort Specification
> Version 1.4 with the following features:
>
> * DisplayPort 1.4a
> * Main Link: 1/2/4 lanes
> * Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps
> * AUX channel 1Mbps
> * Single Stream Transport(SST)
> * Multistream Transport (MST)
> * Type-C support (alternate mode)
> * HDCP 2.2, HDCP 1.3
> * Supports up to 8/10 bits per color component
> * Supports RBG, YCbCr4:4:4, YCbCr4:2:2, YCbCr4:2:0
> * Pixel clock up to 594MHz
> * I2S, SPDIF audio interface
>
> Add library with common helpers to make it can be shared with
> other SoC.
>
> Signed-off-by: Andy Yan <andy....@rock-chips.com>
>
> ---
>
> Changes in v5:
> - Use drm_dp_read_sink_count_cap instead of the private implementation.
>
> Changes in v4:
> - Drop unnecessary header files
> - Switch to devm_drm_bridge_alloc
>
> Changes in v3:
> - Rebase on drm-misc-next
> - Switch to common helpers to power up/down dp link
> - Only pass parameters to phy that should be set
>
> Changes in v2:
> - Fix compile error when build as module
> - Add phy init
> - Only use one dw_dp_link_train_set
> - inline dw_dp_phy_update_vs_emph
> - Use dp_sdp
> - Check return value of drm_modeset_lock
> - Merge code in atomic_pre_enable/mode_fixup to atomic_check
> - Return NULL if can't find a supported output format
> - Fix max_link_rate from plat_data
>
> drivers/gpu/drm/bridge/synopsys/Kconfig | 7 +
> drivers/gpu/drm/bridge/synopsys/Makefile | 1 +
> drivers/gpu/drm/bridge/synopsys/dw-dp.c | 2044 ++++++++++++++++++++++
> include/drm/bridge/dw_dp.h | 20 +
> 4 files changed, 2072 insertions(+)
> create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-dp.c
> create mode 100644 include/drm/bridge/dw_dp.h
> +
> +static int dw_dp_link_parse(struct dw_dp *dp, struct drm_connector
> *connector)
> +{
> + struct dw_dp_link *link = &dp->link;
> + u8 dpcd;
> + int ret;
> +
> + dw_dp_link_reset(link);
> +
> + ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd);
> + if (ret < 0)
> + return ret;
> +
> + drm_dp_read_desc(&dp->aux, &link->desc, drm_dp_is_branch(link->dpcd));
> +
> + if (drm_dp_read_sink_count_cap(connector, link->dpcd, &link->desc)) {
> + ret = drm_dp_read_sink_count(&dp->aux);
> + if (ret < 0)
> + return ret;
> +
> + link->sink_count = ret;
> +
> + /* Dongle connected, but no display */
> + if (!link->sink_count)
> + return -ENODEV;
> + }
> +
> + ret = drm_dp_dpcd_readb(&dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
> &dpcd);
> + if (ret < 0)
> + return ret;
> +
> + link->vsc_sdp_supported = !!(dpcd &
> DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED);
drm_dp_vsc_sdp_supported()
> +
> + link->revision = link->dpcd[DP_DPCD_REV];
> + link->rate = min_t(u32, min(dp->plat_data.max_link_rate,
> + dp->phy->attrs.max_link_rate * 100),
> + drm_dp_max_link_rate(link->dpcd));
> + link->lanes = min_t(u8, phy_get_bus_width(dp->phy),
> + drm_dp_max_lane_count(link->dpcd));
> +
> + link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd);
> + link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd);
> + link->caps.tps4_supported = drm_dp_tps4_supported(link->dpcd);
> + link->caps.fast_training = drm_dp_fast_training_cap(link->dpcd);
> + link->caps.channel_coding = drm_dp_channel_coding_supported(link->dpcd);
> + link->caps.ssc = !!(link->dpcd[DP_MAX_DOWNSPREAD] &
> DP_MAX_DOWNSPREAD_0_5);
> +
> + return 0;
> +}
> +
--
With best wishes
Dmitry
