In analogix_dp_link_start(), &link_train.training_lane[] is used to set phy PE/VS configurations, and buf[] is initialized with the same values to set DPCD DP_TRAINING_LANEx_SET.
It makes sense to reuse &link_train.training_lane[] to set DPCD DP_TRAINING_LANEx_SET, which can remove the redundant assignments and make codes more consice. Signed-off-by: Damon Ding <[email protected]> Tested-by: Marek Szyprowski <[email protected]> --- Changes in v2: - Add Tested-by tag. --- drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index a6d4935234c2..0d7941d37771 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -281,12 +281,8 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp) if (retval < 0) return retval; - for (lane = 0; lane < lane_count; lane++) - buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | - DP_TRAIN_VOLTAGE_SWING_LEVEL_0; - - retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, - lane_count); + retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, + dp->link_train.training_lane, lane_count); if (retval < 0) return retval; -- 2.34.1
