Hi,
On 9/15/25 13:27, Maxime Ripard wrote:
On Thu, Sep 11, 2025 at 04:37:15PM +0530, Swamil Jain wrote:
From: Jayesh Choudhary <[email protected]>
Since OLDI consumes DSS VP clock directly as serial clock, mode_valid()
check cannot be performed in tidss driver which should be checked
in OLDI driver.
Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support")
Tested-by: Michael Walle <[email protected]>
Reviewed-by: Devarsh Thakkar <[email protected]>
Signed-off-by: Jayesh Choudhary <[email protected]>
Signed-off-by: Swamil Jain <[email protected]>
---
drivers/gpu/drm/tidss/tidss_oldi.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c
b/drivers/gpu/drm/tidss/tidss_oldi.c
index 7ecbb2c3d0a2..ada691839ef3 100644
--- a/drivers/gpu/drm/tidss/tidss_oldi.c
+++ b/drivers/gpu/drm/tidss/tidss_oldi.c
@@ -309,6 +309,26 @@ static u32 *tidss_oldi_atomic_get_input_bus_fmts(struct
drm_bridge *bridge,
return input_fmts;
}
+static int tidss_oldi_atomic_check(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge);
+ struct drm_display_mode *adjusted_mode;
+ unsigned long round_clock;
+
+ adjusted_mode = &crtc_state->adjusted_mode;
+ round_clock = clk_round_rate(oldi->serial, adjusted_mode->clock * 7 *
1000);
+ /*
+ * To keep the check consistent with dispc_vp_set_clk_rate(),
+ * we use the same 5% check here.
+ */
+ if (dispc_pclk_diff(adjusted_mode->clock * 7 * 1000, round_clock) > 5)
+ return -EINVAL;
+ return 0;
+}
+
If you're introducing that check to tidss, please use .5% like everyone
else. I understand that you don't want to change tilcdc to avoid any
regression, but that's not the case here
This is just to make the tolerance check consistent for mode validation
and setting clock rate. This patch isn't introducing anything new, we
are following this as dispc_vp_set_clk_rate() and
tidss_oldi_set_serial_clk() are already checking for 5% tolerance while
setting clock. To remove/modify, this needs extensive testing with other
K3 and K2G SoCs and can be handled as a separate patch.
Regards,
Swamil
Maxime
