Let the TTM pool allocator know that we can afford for it to expend less effort for satisfying contiguous allocations larger than 2MiB. The latter is the maximum relevant PTE entry size and the driver and hardware are happy to get larger blocks only opportunistically.
Signed-off-by: Tvrtko Ursulin <[email protected]> Cc: Christian König <[email protected]> Cc: Thadeu Lima de Souza Cascardo <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 428265046815..7d7b91e07a47 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1812,6 +1812,9 @@ static int amdgpu_ttm_pools_init(struct amdgpu_device *adev) { int i; + ttm_pool_set_max_beneficial_order(&adev->mman.bdev.pool, + get_order(2 * SZ_1M)); + if (!adev->gmc.is_app_apu || !adev->gmc.num_mem_partitions) return 0; @@ -1825,6 +1828,8 @@ static int amdgpu_ttm_pools_init(struct amdgpu_device *adev) ttm_pool_init(&adev->mman.ttm_pools[i], adev->dev, adev->gmc.mem_partitions[i].numa.node, false, false); + ttm_pool_set_max_beneficial_order(&adev->mman.ttm_pools[i], + get_order(2 * SZ_1M)); } return 0; } -- 2.48.0
