The CSUS clock is a clock gate for the output clock signal primarily sourced from the VI_SENSOR clock. This clock signal is used as an input MCLK clock for cameras.
Unlike later Tegra SoCs, the Tegra 20 can change its CSUS parent, which is why csus_mux is added in a similar way to how CDEV1 and CDEV2 are handled. Signed-off-by: Svyatoslav Ryhel <[email protected]> --- drivers/clk/tegra/clk-tegra114.c | 7 ++++++- drivers/clk/tegra/clk-tegra20.c | 20 +++++++++++++------- drivers/clk/tegra/clk-tegra30.c | 7 ++++++- drivers/pinctrl/tegra/pinctrl-tegra20.c | 7 +++++++ 4 files changed, 32 insertions(+), 9 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index 186b0b81c1ec..00282b0d3763 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -691,7 +691,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = { [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true }, [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true }, [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true }, - [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true }, [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true }, [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true }, [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true }, @@ -1047,6 +1046,12 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base, 0, 82, periph_clk_enb_refcnt); clks[TEGRA114_CLK_DSIB] = clk; + /* csus */ + clk = tegra_clk_register_periph_gate("csus", "vi_sensor", 0, + clk_base, 0, TEGRA114_CLK_CSUS, + periph_clk_enb_refcnt); + clks[TEGRA114_CLK_CSUS] = clk; + /* emc mux */ clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, ARRAY_SIZE(mux_pllmcp_clkm), diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 2c58ce25af75..d8d5afeb6f9b 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -530,7 +530,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = { [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true }, [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true }, [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true }, - [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true }, [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true }, [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true }, [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true }, @@ -834,6 +833,12 @@ static void __init tegra20_periph_clk_init(void) clk_base, 0, 93, periph_clk_enb_refcnt); clks[TEGRA20_CLK_CDEV2] = clk; + /* csus */ + clk = tegra_clk_register_periph_gate("csus", "csus_mux", 0, + clk_base, 0, TEGRA20_CLK_CSUS, + periph_clk_enb_refcnt); + clks[TEGRA20_CLK_CSUS] = clk; + for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { data = &tegra_periph_clk_list[i]; clk = tegra_clk_register_periph_data(clk_base, data); @@ -1093,14 +1098,15 @@ static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec, hw = __clk_get_hw(clk); /* - * Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent - * clock is created by the pinctrl driver. It is possible for clk user - * to request these clocks before pinctrl driver got probed and hence - * user will get an orphaned clock. That might be undesirable because - * user may expect parent clock to be enabled by the child. + * Tegra20 CDEV1, CDEV2 and CSUS clocks are a bit special case, their + * parent clock is created by the pinctrl driver. It is possible for + * clk user to request these clocks before pinctrl driver got probed + * and hence user will get an orphaned clock. That might be undesirable + * because user may expect parent clock to be enabled by the child. */ if (clkspec->args[0] == TEGRA20_CLK_CDEV1 || - clkspec->args[0] == TEGRA20_CLK_CDEV2) { + clkspec->args[0] == TEGRA20_CLK_CDEV2 || + clkspec->args[0] == TEGRA20_CLK_CSUS) { parent_hw = clk_hw_get_parent(hw); if (!parent_hw) return ERR_PTR(-EPROBE_DEFER); diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 82a8cb9545eb..ca367184e185 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -779,7 +779,6 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = { [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true }, [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true }, [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true }, - [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true }, [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true }, [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true }, [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true }, @@ -1008,6 +1007,12 @@ static void __init tegra30_periph_clk_init(void) 0, 48, periph_clk_enb_refcnt); clks[TEGRA30_CLK_DSIA] = clk; + /* csus */ + clk = tegra_clk_register_periph_gate("csus", "vi_sensor", 0, + clk_base, 0, TEGRA30_CLK_CSUS, + periph_clk_enb_refcnt); + clks[TEGRA30_CLK_CSUS] = clk; + /* pcie */ clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, 70, periph_clk_enb_refcnt); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c index 737fc2000f66..437e0ac091cc 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra20.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c @@ -2230,6 +2230,10 @@ static const char *cdev2_parents[] = { "dev2_osc_div", "hclk", "pclk", "pll_p_out4", }; +static const char *csus_parents[] = { + "pll_c_out1", "pll_p_out2", "pll_p_out3", "vi_sensor", +}; + static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev) { struct tegra_pmx *pmx = platform_get_drvdata(pdev); @@ -2239,6 +2243,9 @@ static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev) clk_register_mux(NULL, "cdev2_mux", cdev2_parents, 4, 0, pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL); + + clk_register_mux(NULL, "csus_mux", csus_parents, 4, 0, + pmx->regs[1] + 0x8, 6, 2, CLK_MUX_READ_ONLY, NULL); } static int tegra20_pinctrl_probe(struct platform_device *pdev) -- 2.48.1
