On Thu, Oct 02, 2025 at 03:00:03AM +0530, Akhil P Oommen wrote: > > > On 9/30/2025 1:05 PM, Dmitry Baryshkov wrote: > > On Tue, Sep 30, 2025 at 11:18:16AM +0530, Akhil P Oommen wrote: > > > A8x GMU configuration are very similar to A7x. Unfortunately, there are > > > minor shuffling in the register offsets in the GMU CX register region. > > > Apart from that, there is a new HFI message support to pass table like > > > data. This patch adds support for perf table using this new HFI > > > message. > > > > > > Apart from that, there is a minor rework in a6xx_gmu_rpmh_arc_votes_init() > > > to simplify handling of MxG to MxA fallback along with the additional > > > calculations for the new dependency vote. > > > > I'm sorry, I've sent it too early. This looks like a description > > of a not-that-related change which should be split to a separate commit. > > > > > > > > Signed-off-by: Akhil P Oommen <[email protected]> > > > --- > > > @@ -555,6 +557,11 @@ static inline int adreno_is_a7xx(struct adreno_gpu > > > *gpu) > > > adreno_is_a740_family(gpu); > > > } > > > +static inline int adreno_is_a8xx(struct adreno_gpu *gpu) > > > +{ > > > + return gpu->info->family >= ADRENO_8XX_GEN1; > > > +} > > > > This and the register mask updates can go to a separate commit. > > Which mask update exactly?
I'm sorry. Changes in register XML files, adding A8XX into the picture. > > I can split out the hfi table addition and arc table updates into 2 separate > patches. That one too. > > -Akhil. > > > > > > + > > > /* Put vm_start above 32b to catch issues with not setting xyz_BASE_HI > > > */ > > > #define ADRENO_VM_START 0x100000000ULL > > > u64 adreno_private_vm_size(struct msm_gpu *gpu); > > > diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml > > > b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml > > > index > > > 09b8a0b9c0de7615f7e7e6364c198405a498121a..5dce7934056dd6472c368309b4894f0ed4a4d960 > > > 100644 > > > --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml > > > +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml > > > @@ -66,10 +66,15 @@ > > > xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ > > > rules-fd.xsd"> > > > <reg32 offset="0x1f81c" name="GMU_CM3_FW_INIT_RESULT"/> > > > <reg32 offset="0x1f82d" name="GMU_CM3_CFG"/> > > > <reg32 offset="0x1f840" name="GMU_CX_GMU_POWER_COUNTER_ENABLE"/> > > > + <reg32 offset="0x1fc10" name="GMU_CX_GMU_POWER_COUNTER_ENABLE" > > > variants="A8XX"/> > > > <reg32 offset="0x1f841" > > > name="GMU_CX_GMU_POWER_COUNTER_SELECT_0"/> > > > <reg32 offset="0x1f842" > > > name="GMU_CX_GMU_POWER_COUNTER_SELECT_1"/> > > > + <reg32 offset="0x1fc40" name="GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_0" > > > variants="A8XX-"/> > > > + <reg32 offset="0x1fc41" name="GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_1" > > > variants="A8XX-"/> > > > <reg32 offset="0x1f844" > > > name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L"/> > > > + <reg32 offset="0x1fca0" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L" > > > variants="A8XX-"/> > > > <reg32 offset="0x1f845" > > > name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H"/> > > > + <reg32 offset="0x1fca1" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H" > > > variants="A8XX-"/> > > > <reg32 offset="0x1f846" > > > name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L"/> > > > <reg32 offset="0x1f847" > > > name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H"/> > > > <reg32 offset="0x1f848" > > > name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L"/> -- With best wishes Dmitry
