On Sat, Oct 11, 2025 at 06:51:44PM +0200, Marek Vasut wrote: > Freescale i.MX95 SoC embeds a Synopsys Designware MIPI DSI host > controller and a Synopsys Designware MIPI DPHY. Unlike the i.MX93 > PHY, the i.MX95 PHY uses more syscon interfaces to configure the > PHY.
Any common driver for Synopsys Designware MIPI DSI, suppose many vendor use this IP? > > Signed-off-by: Marek Vasut <[email protected]> > --- > Cc: Abel Vesa <[email protected]> > Cc: Conor Dooley <[email protected]> > Cc: Fabio Estevam <[email protected]> > Cc: Krzysztof Kozlowski <[email protected]> > Cc: Laurent Pinchart <[email protected]> > Cc: Liu Ying <[email protected]> > Cc: Lucas Stach <[email protected]> > Cc: Peng Fan <[email protected]> > Cc: Pengutronix Kernel Team <[email protected]> > Cc: Rob Herring <[email protected]> > Cc: Shawn Guo <[email protected]> > Cc: Thomas Zimmermann <[email protected]> > Cc: [email protected] > Cc: [email protected] > Cc: [email protected] > Cc: [email protected] > Cc: [email protected] > --- > .../display/bridge/fsl,imx93-mipi-dsi.yaml | 48 +++++++++++++++++-- > 1 file changed, 43 insertions(+), 5 deletions(-) > > diff --git > a/Documentation/devicetree/bindings/display/bridge/fsl,imx93-mipi-dsi.yaml > b/Documentation/devicetree/bindings/display/bridge/fsl,imx93-mipi-dsi.yaml > index d6e51d0cf5464..388301c4f95c1 100644 > --- a/Documentation/devicetree/bindings/display/bridge/fsl,imx93-mipi-dsi.yaml > +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx93-mipi-dsi.yaml > @@ -14,12 +14,11 @@ description: | > Designware MIPI DPHY embedded in Freescale i.MX93 SoC. Some configurations > and extensions to them are controlled by i.MX93 media blk-ctrl. > > -allOf: > - - $ref: snps,dw-mipi-dsi.yaml# > - > properties: > compatible: > - const: fsl,imx93-mipi-dsi > + enum: > + - fsl,imx93-mipi-dsi > + - fsl,imx95-mipi-dsi > > clocks: > items: > @@ -46,13 +45,52 @@ properties: > controller and MIPI DPHY PLL related configurations through PLL SoC > interface. > > + fsl,disp-master-csr: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + i.MX95 Display Master CSR is a syscon which includes registers to > + control DSI clock settings, clock gating, and pixel link select. why not go through standard phy interface? > + > + fsl,disp-stream-csr: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + i.MX95 Display Stream CSR is a syscon which includes configuration > + and status registers for the DSI host. why not go through standard phy interface? Frank > + > + fsl,mipi-combo-phy-csr: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + i.MX95 Display Stream CSR is a syscon which configuration and status > + registers for the MIPI Tx DPHY module in the Camera domain. > + > power-domains: > maxItems: 1 > > +allOf: > + - $ref: snps,dw-mipi-dsi.yaml# > + - if: > + properties: > + compatible: > + contains: > + const: fsl,imx93-mipi-dsi > + then: > + required: > + - fsl,media-blk-ctrl > + > + - if: > + properties: > + compatible: > + contains: > + const: fsl,imx95-mipi-dsi > + then: > + required: > + - fsl,disp-master-csr > + - fsl,disp-stream-csr > + - fsl,mipi-combo-phy-csr > + > required: > - compatible > - interrupts > - - fsl,media-blk-ctrl > - power-domains > > unevaluatedProperties: false > -- > 2.51.0 >
