Previously, the max count for the GPFIFO ring buffer was hardcoded in two different places.
This patch adds a new function nouveau_channel_get_gpfifo_entries_count to share the logic between the two side of the codebase allowing us to later on increase the limit. Signed-off-by: Mary Guillemard <[email protected]> --- drivers/gpu/drm/nouveau/nouveau_abi16.c | 15 +++++++++++++-- drivers/gpu/drm/nouveau/nouveau_chan.c | 3 ++- drivers/gpu/drm/nouveau/nouveau_chan.h | 12 ++++++++++++ drivers/gpu/drm/nouveau/nouveau_dma.h | 3 --- 4 files changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index a3ba07fc48a0..a5445e97179f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -232,15 +232,26 @@ nouveau_abi16_fini(struct nouveau_abi16 *abi16) static inline int getparam_dma_ib_max(struct nvif_device *device) { - const struct nvif_mclass dmas[] = { + const struct nvif_mclass hosts[] = { { NV03_CHANNEL_DMA, 0 }, { NV10_CHANNEL_DMA, 0 }, { NV17_CHANNEL_DMA, 0 }, { NV40_CHANNEL_DMA, 0 }, {} }; + int cid; + u32 res; - return nvif_mclass(&device->object, dmas) < 0 ? NV50_DMA_IB_MAX : 0; + cid = nvif_mclass(&device->object, hosts); + if (cid < 0) + res = NV50_CHANNEL_GPFIFO_ENTRIES_MAX_COUNT; + else + res = nouveau_channel_get_gpfifo_entries_count(hosts[cid].oclass); + + if (res == 0) + return 0; + + return res - 1; } int diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index b646212a34b3..8695b5d6aefc 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -274,7 +274,7 @@ nouveau_channel_ctor(struct nouveau_cli *cli, bool priv, u64 runm, struct nouveau_channel *chan; const u64 plength = 0x10000; const u64 ioffset = plength; - const u64 ilength = 0x02000; + u64 ilength; int cid, ret; u64 size; @@ -282,6 +282,7 @@ nouveau_channel_ctor(struct nouveau_cli *cli, bool priv, u64 runm, if (cid < 0) return cid; + ilength = nouveau_channel_get_gpfifo_entries_count(hosts[cid].oclass) * 8; if (hosts[cid].oclass < NV50_CHANNEL_GPFIFO) size = plength; else diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.h b/drivers/gpu/drm/nouveau/nouveau_chan.h index 9839de8da985..294d061497c0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.h +++ b/drivers/gpu/drm/nouveau/nouveau_chan.h @@ -4,6 +4,7 @@ #include <nvif/object.h> #include <nvif/event.h> #include <nvif/chan.h> +#include <nvif/class.h> struct nvif_device; struct nouveau_channel { @@ -65,6 +66,17 @@ void nouveau_channel_del(struct nouveau_channel **); int nouveau_channel_idle(struct nouveau_channel *); void nouveau_channel_kill(struct nouveau_channel *); +/* Maximum GPFIFO entries per channel. */ +#define NV50_CHANNEL_GPFIFO_ENTRIES_MAX_COUNT (0x02000 / 8) + +static inline u32 nouveau_channel_get_gpfifo_entries_count(u32 oclass) +{ + if (oclass < NV50_CHANNEL_GPFIFO) + return 0; + + return NV50_CHANNEL_GPFIFO_ENTRIES_MAX_COUNT; +} + extern int nouveau_vram_pushbuf; #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index c25ef9a54b9f..7f8445014e4d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -47,9 +47,6 @@ int nouveau_dma_wait(struct nouveau_channel *, int size); /* Maximum push buffer size. */ #define NV50_DMA_PUSH_MAX_LENGTH 0x7fffff -/* Maximum IBs per ring. */ -#define NV50_DMA_IB_MAX ((0x02000 / 8) - 1) - /* Object handles - for stuff that's doesn't use handle == oclass. */ enum { NvDmaFB = 0x80000002, -- 2.52.0
