On Fri, Jan 09, 2026 at 02:11:19PM -0500, Connor Abbott wrote: > On Thu, Jan 8, 2026 at 9:22 AM Konrad Dybcio <[email protected]> wrote: > > > > SMEM allows the OS to retrieve information about the DDR memory. > > Among that information, is a semi-magic value called 'HBB', or Highest > > Bank address Bit, which multimedia drivers (for hardware like Adreno > > and MDSS) must retrieve in order to program the IP blocks correctly. > > > > This series introduces an API to retrieve that value, uses it in the > > aforementioned programming sequences and exposes available DDR > > frequencies in debugfs (to e.g. pass to aoss_qmp debugfs). More > > information can be exposed in the future, as needed. > > > > Patch 3 should really be merged after 1&2 > > No. The HBB value currently returned by the bootloader is *not* always > the same as what we use currently, because some SoCs (like SM8250) > with the same DT ship with multiple different DRAM configurations and > we've been using a sub-optimal value the whole time. After all, that's > the whole point of using the bootloader value. But patches 1&2 will > only make the DPU use the bootloader value for HBB, not the GPU. So on > one of the affected SoCs, it will introduce a mismatch. You can't > change anything until the GPU side uses the new ubwc config as its > source of truth.
Which, unfortunately, also means that Iris / Venus must also start using the UBWC config API beforehand. -- With best wishes Dmitry
