Hi Geert,
Thanks for your review.
On Fri, Jan 09, 2026 at 07:38:40PM +0100, Geert Uytterhoeven wrote:
> Hi Tommaso,
>
> On Wed, 26 Nov 2025 at 15:10, Tommaso Merciai
> <[email protected]> wrote:
> > Add support for the SMUX2_DSI0_CLK and SMUX2_DSI1_CLK clock muxes
> > present on the r9a09g047 SoC.
> >
> > These muxes select between CDIV7_DSI{0,1}_CLK and CSDIV_2to16_PLLDSI{0,1}
> > using the CPG_SSEL3 register (SELCTL0 and SELCTL1 bits).
> >
> > According to the hardware manual, when LVDS0 or LVDS1 outputs are used,
> > SELCTL0 or SELCTL1 must be set accordingly.
> >
> > Signed-off-by: Tommaso Merciai <[email protected]>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> > @@ -64,6 +64,8 @@ enum clk_ids {
> > CLK_SMUX2_GBE0_RXCLK,
> > CLK_SMUX2_GBE1_TXCLK,
> > CLK_SMUX2_GBE1_RXCLK,
> > + CLK_SMUX2_DSI0_CLK,
> > + CLK_SMUX2_DSI1_CLK,
>
> Please move these up, before CLK_SMUX2_GBE0_TXCLK.
Ack.
>
> > CLK_PLLDTY_DIV16,
> > CLK_PLLVDO_CRU0,
> > CLK_PLLVDO_GPU,
> > @@ -143,6 +145,8 @@ RZG3E_CPG_PLL_DSI1_LIMITS(rzg3e_cpg_pll_dsi1_limits);
> > #define PLLDSI1 PLL_PACK_LIMITS(0x160, 1, 1,
> > &rzg3e_cpg_pll_dsi1_limits)
> >
> > /* Mux clock tables */
> > +static const char * const smux2_dsi0_clk[] = { ".plldsi0_div7",
> > ".plldsi0_csdiv" };
> > +static const char * const smux2_dsi1_clk[] = { ".plldsi1_div7",
> > ".plldsi1_csdiv" };
> > static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0",
> > "et0_rxclk" };
> > static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0",
> > "et0_txclk" };
> > static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1",
> > "et1_rxclk" };
> > @@ -218,6 +222,10 @@ static const struct cpg_core_clk r9a09g047_core_clks[]
> > __initconst = {
> > CSDIV1_DIVCTL3, dtable_2_16_plldsi),
> > DEF_FIXED(".plldsi0_div7", CLK_PLLDSI0_DIV7, CLK_PLLDSI0, 1, 7),
> > DEF_FIXED(".plldsi1_div7", CLK_PLLDSI1_DIV7, CLK_PLLDSI1, 1, 7),
> > + DEF_PLLDSI_SMUX(".smux2_dsi0_clk", CLK_SMUX2_DSI0_CLK,
> > + SSEL3_SELCTL0, smux2_dsi0_clk),
> > + DEF_PLLDSI_SMUX(".smux2_dsi1_clk", CLK_SMUX2_DSI1_CLK,
> > + SSEL3_SELCTL1, smux2_dsi1_clk),
>
> Why can't these use the existing DEF_SMUX()?
Same comment of [0].
Kind Regards,
Tommaso
[0] https://patchwork.kernel.org/comment/26730109/
> >
> > /* Core Clocks */
> > DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
