From: Chris Morgan <[email protected]> Add support for both panels used in the Anbernic RG-DS. These panels are physically identical and differ only with a single instruction in the init sequence. The init sequence commands suggest it uses an identical controller as the jd9365da.
Additionally, allow specifying per-panel dsi->mode_flags that can override the default values. Signed-off-by: Chris Morgan <[email protected]> Co-developed-by: Alexander Weinzerl <[email protected]> Signed-off-by: Alexander Weinzerl <[email protected]> --- .../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 271 +++++++++++++++++- 1 file changed, 269 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c index 063ed9646d53..5386a06fcd08 100644 --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -33,6 +33,7 @@ struct jadard_panel_desc { unsigned int backlight_off_to_display_off_delay_ms; unsigned int display_off_to_enter_sleep_delay_ms; unsigned int enter_sleep_to_reset_down_delay_ms; + unsigned long mode_flags; }; struct jadard { @@ -1113,6 +1114,258 @@ static const struct jadard_panel_desc melfas_lmfbx101117480_desc = { .enter_sleep_to_reset_down_delay_ms = 100, }; +static int anbernic_rgds_init_cmds(struct jadard *jadard) +{ + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; + struct drm_panel *panel = &jadard->panel; + + jd9365da_switch_page(&dsi_ctx, 0x0); + + jadard_enable_standard_cmds(&dsi_ctx); + + jd9365da_switch_page(&dsi_ctx, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x6a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x6a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xbf); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xbf); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe); + + if (of_device_is_compatible(panel->dev->of_node, + "anbernic,rg-ds-display-top")) + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x05); + else + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09); + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0xf7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x3c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x11); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x78); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x6d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x56); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x34); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x2f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x22); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x0c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x24); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x24); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x25); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x33); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x3a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x2d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x1b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x0b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x56); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x34); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x2f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x22); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x0c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x24); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x24); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x25); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x33); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x3a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x2d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x1b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00); + + jd9365da_switch_page(&dsi_ctx, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x5e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x4a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x4a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x5e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x4b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x4b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x1e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x0b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x0b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x1e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x30); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0xe9); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x0b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0xe9); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xda); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0xfc); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x83, 0xf4); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x87, 0x10); + + jd9365da_switch_page(&dsi_ctx, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x58); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x0f); + + jd9365da_switch_page(&dsi_ctx, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1d); + + jd9365da_switch_page(&dsi_ctx, 0x00); + mipi_dsi_msleep(&dsi_ctx, 120); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 10); + + return dsi_ctx.accum_err; +}; + +static const struct jadard_panel_desc anbernic_rgds_display_desc = { + .mode = { + .clock = (640 + 260 + 220 + 260) * (480 + 10 + 2 + 16) * 60 / 1000, + + .hdisplay = 640, + .hsync_start = 640 + 260, + .hsync_end = 640 + 260 + 220, + .htotal = 640 + 260 + 220 + 260, + + .vdisplay = 480, + .vsync_start = 480 + 10, + .vsync_end = 480 + 10 + 2, + .vtotal = 480 + 10 + 2 + 16, + + .width_mm = 68, + .height_mm = 87, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, + }, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .init = anbernic_rgds_init_cmds, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM, +}; + static int jadard_dsi_probe(struct mipi_dsi_device *dsi) { struct device *dev = &dsi->dev; @@ -1126,8 +1379,14 @@ static int jadard_dsi_probe(struct mipi_dsi_device *dsi) return PTR_ERR(jadard); desc = of_device_get_match_data(dev); - dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_NO_EOT_PACKET; + + if (desc->mode_flags) + dsi->mode_flags = desc->mode_flags; + else + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_NO_EOT_PACKET; + dsi->format = desc->format; dsi->lanes = desc->lanes; @@ -1176,6 +1435,14 @@ static void jadard_dsi_remove(struct mipi_dsi_device *dsi) } static const struct of_device_id jadard_of_match[] = { + { + .compatible = "anbernic,rg-ds-display-bottom", + .data = &anbernic_rgds_display_desc + }, + { + .compatible = "anbernic,rg-ds-display-top", + .data = &anbernic_rgds_display_desc + }, { .compatible = "chongzhou,cz101b4001", .data = &cz101b4001_desc -- 2.43.0
