On 07/08/2011 09:51 AM, Alex Deucher wrote:
> evergreen+ asics have 2-6 crtcs. Don't access crtc registers
> for crtc regs that don't exist as they have very high latency
> and may cause problems on some asics. The previous code missed
> a few cases and was not fine grained enough (missed the 4 crtc
> case for example).
>
> Fixes:
> https://bugs.freedesktop.org/show_bug.cgi?id=38800
>
> Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
> Reviewed-by: Michel D?nzer <michel at daenzer.net>
> ---
> drivers/gpu/drm/radeon/evergreen.c | 159
> ++++++++++++++++++++++--------------
> 1 files changed, 98 insertions(+), 61 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/evergreen.c
> b/drivers/gpu/drm/radeon/evergreen.c
> index e8a5ffb..bf2493b 100644
> --- a/drivers/gpu/drm/radeon/evergreen.c
> +++ b/drivers/gpu/drm/radeon/evergreen.c
> @@ -985,17 +985,19 @@ void evergreen_mc_stop(struct radeon_device *rdev,
> struct evergreen_mc_save *sav
> {
> save->vga_control[0] = RREG32(D1VGA_CONTROL);
> save->vga_control[1] = RREG32(D2VGA_CONTROL);
> - save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
> - save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
> - save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
> - save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
> save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
> save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
> save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL +
> EVERGREEN_CRTC0_REGISTER_OFFSET);
> save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL +
> EVERGREEN_CRTC1_REGISTER_OFFSET);
> - if (!(rdev->flags & RADEON_IS_IGP)) {
> + if (rdev->num_crtc >= 4) {
> + save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
> + save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
> save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL +
> EVERGREEN_CRTC2_REGISTER_OFFSET);
> save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL +
> EVERGREEN_CRTC3_REGISTER_OFFSET);
> + }
> + if (rdev->num_crtc >= 6) {
> + save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
> + save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
> save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL +
> EVERGREEN_CRTC4_REGISTER_OFFSET);
> save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL +
> EVERGREEN_CRTC5_REGISTER_OFFSET);
> }
> @@ -1004,35 +1006,45 @@ void evergreen_mc_stop(struct radeon_device *rdev,
> struct evergreen_mc_save *sav
> WREG32(VGA_RENDER_CONTROL, 0);
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
> - if (!(rdev->flags & RADEON_IS_IGP)) {
> + if (rdev->num_crtc >= 4) {
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
> EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
> EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
> + }
> + if (rdev->num_crtc >= 6) {
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
> EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
> EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
> }
> WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
> WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
> - if (!(rdev->flags & RADEON_IS_IGP)) {
> + if (rdev->num_crtc >= 4) {
> WREG32(EVERGREEN_CRTC_CONTROL +
> EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
> WREG32(EVERGREEN_CRTC_CONTROL +
> EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
> + }
> + if (rdev->num_crtc >= 6) {
> WREG32(EVERGREEN_CRTC_CONTROL +
> EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
> WREG32(EVERGREEN_CRTC_CONTROL +
> EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
> }
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
> - if (!(rdev->flags & RADEON_IS_IGP)) {
> + if (rdev->num_crtc >= 4) {
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
> EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
> EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
> + }
> + if (rdev->num_crtc >= 6) {
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
> EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
> EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
> }
>
> WREG32(D1VGA_CONTROL, 0);
> WREG32(D2VGA_CONTROL, 0);
> - WREG32(EVERGREEN_D3VGA_CONTROL, 0);
> - WREG32(EVERGREEN_D4VGA_CONTROL, 0);
> - WREG32(EVERGREEN_D5VGA_CONTROL, 0);
> - WREG32(EVERGREEN_D6VGA_CONTROL, 0);
> + if (rdev->num_crtc >= 4) {
> + WREG32(EVERGREEN_D3VGA_CONTROL, 0);
> + WREG32(EVERGREEN_D4VGA_CONTROL, 0);
> + }
> + if (rdev->num_crtc >= 6) {
> + WREG32(EVERGREEN_D5VGA_CONTROL, 0);
> + WREG32(EVERGREEN_D6VGA_CONTROL, 0);
> + }
> }
>
> void evergreen_mc_resume(struct radeon_device *rdev, struct
> evergreen_mc_save *save)
> @@ -1055,7 +1067,7 @@ void evergreen_mc_resume(struct radeon_device *rdev,
> struct evergreen_mc_save *s
> WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS +
> EVERGREEN_CRTC1_REGISTER_OFFSET,
> (u32)rdev->mc.vram_start);
>
> - if (!(rdev->flags & RADEON_IS_IGP)) {
> + if (rdev->num_crtc >= 4) {
> WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH +
> EVERGREEN_CRTC2_REGISTER_OFFSET,
> upper_32_bits(rdev->mc.vram_start));
> WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH +
> EVERGREEN_CRTC2_REGISTER_OFFSET,
> @@ -1073,7 +1085,8 @@ void evergreen_mc_resume(struct radeon_device *rdev,
> struct evergreen_mc_save *s
> (u32)rdev->mc.vram_start);
> WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS +
> EVERGREEN_CRTC3_REGISTER_OFFSET,
> (u32)rdev->mc.vram_start);
> -
> + }
> + if (rdev->num_crtc >= 6) {
> WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH +
> EVERGREEN_CRTC4_REGISTER_OFFSET,
> upper_32_bits(rdev->mc.vram_start));
> WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH +
> EVERGREEN_CRTC4_REGISTER_OFFSET,
> @@ -1101,31 +1114,41 @@ void evergreen_mc_resume(struct radeon_device *rdev,
> struct evergreen_mc_save *s
> /* Restore video state */
> WREG32(D1VGA_CONTROL, save->vga_control[0]);
> WREG32(D2VGA_CONTROL, save->vga_control[1]);
> - WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
> - WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
> - WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
> - WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
> + if (rdev->num_crtc >= 4) {
> + WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
> + WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
> + }
> + if (rdev->num_crtc >= 6) {
> + WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
> + WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
> + }
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
> - if (!(rdev->flags & RADEON_IS_IGP)) {
> + if (rdev->num_crtc >= 4) {
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
> EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
> EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
> + }
> + if (rdev->num_crtc >= 4) {
Should be six here?
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
> EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
> EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
> }
> WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
> save->crtc_control[0]);
> WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
> save->crtc_control[1]);
> - if (!(rdev->flags & RADEON_IS_IGP)) {
> + if (rdev->num_crtc >= 4) {
> WREG32(EVERGREEN_CRTC_CONTROL +
> EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
> WREG32(EVERGREEN_CRTC_CONTROL +
> EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
> + }
> + if (rdev->num_crtc >= 6) {
> WREG32(EVERGREEN_CRTC_CONTROL +
> EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
> WREG32(EVERGREEN_CRTC_CONTROL +
> EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
> }
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
> - if (!(rdev->flags & RADEON_IS_IGP)) {
> + if (rdev->num_crtc >= 4) {
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
> EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
> EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
> + }
> + if (rdev->num_crtc >= 6) {
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
> EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
> WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
> EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
> }
> @@ -2417,18 +2440,22 @@ void evergreen_disable_interrupt_state(struct
> radeon_device *rdev)
> WREG32(GRBM_INT_CNTL, 0);
> WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
> WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
> - if (!(rdev->flags & RADEON_IS_IGP)) {
> + if (rdev->num_crtc >= 4) {
> WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
> WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
> + }
> + if (rdev->num_crtc >= 6) {
> WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
> WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
> }
>
> WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
> WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
> - if (!(rdev->flags & RADEON_IS_IGP)) {
> + if (rdev->num_crtc >= 4) {
> WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
> WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
> + }
> + if (rdev->num_crtc >= 6) {
> WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
> WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
> }
> @@ -2547,19 +2574,25 @@ int evergreen_irq_set(struct radeon_device *rdev)
>
> WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
> WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
> - if (!(rdev->flags & RADEON_IS_IGP)) {
> + if (rdev->num_crtc >= 4) {
> WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
> WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
> + }
> + if (rdev->num_crtc >= 6) {
> WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
> WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
> }
>
> WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
> WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
> - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
> - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
> - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
> - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
> + if (rdev->num_crtc >= 4) {
> + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
> grph3);
> + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
> grph4);
> + }
> + if (rdev->num_crtc >= 6) {
> + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
> grph5);
> + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
> grph6);
> + }
>
> WREG32(DC_HPD1_INT_CONTROL, hpd1);
> WREG32(DC_HPD2_INT_CONTROL, hpd2);
> @@ -2583,53 +2616,57 @@ static inline void evergreen_irq_ack(struct
> radeon_device *rdev)
> rdev->irq.stat_regs.evergreen.disp_int_cont5 =
> RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
> rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS +
> EVERGREEN_CRTC0_REGISTER_OFFSET);
> rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS +
> EVERGREEN_CRTC1_REGISTER_OFFSET);
> - rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS +
> EVERGREEN_CRTC2_REGISTER_OFFSET);
> - rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS +
> EVERGREEN_CRTC3_REGISTER_OFFSET);
> - rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS +
> EVERGREEN_CRTC4_REGISTER_OFFSET);
> - rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS +
> EVERGREEN_CRTC5_REGISTER_OFFSET);
> + if (rdev->num_crtc >= 4) {
> + rdev->irq.stat_regs.evergreen.d3grph_int =
> RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
> + rdev->irq.stat_regs.evergreen.d4grph_int =
> RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
> + }
> + if (rdev->num_crtc >= 6) {
> + rdev->irq.stat_regs.evergreen.d5grph_int =
> RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
> + rdev->irq.stat_regs.evergreen.d6grph_int =
> RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
> + }
>
> if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
> WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
> GRPH_PFLIP_INT_CLEAR);
> if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
> WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,
> GRPH_PFLIP_INT_CLEAR);
> - if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
> - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
> GRPH_PFLIP_INT_CLEAR);
> - if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
> - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
> GRPH_PFLIP_INT_CLEAR);
> - if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
> - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
> GRPH_PFLIP_INT_CLEAR);
> - if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
> - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,
> GRPH_PFLIP_INT_CLEAR);
> -
> if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
> WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
> VBLANK_ACK);
> if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
> WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
> VLINE_ACK);
> -
> if (rdev->irq.stat_regs.evergreen.disp_int_cont &
> LB_D2_VBLANK_INTERRUPT)
> WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,
> VBLANK_ACK);
> if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
> WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,
> VLINE_ACK);
>
> - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 &
> LB_D3_VBLANK_INTERRUPT)
> - WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
> VBLANK_ACK);
> - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 &
> LB_D3_VLINE_INTERRUPT)
> - WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
> VLINE_ACK);
> -
> - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 &
> LB_D4_VBLANK_INTERRUPT)
> - WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
> VBLANK_ACK);
> - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 &
> LB_D4_VLINE_INTERRUPT)
> - WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
> VLINE_ACK);
> -
> - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 &
> LB_D5_VBLANK_INTERRUPT)
> - WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
> VBLANK_ACK);
> - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 &
> LB_D5_VLINE_INTERRUPT)
> - WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
> VLINE_ACK);
> -
> - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 &
> LB_D6_VBLANK_INTERRUPT)
> - WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,
> VBLANK_ACK);
> - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 &
> LB_D6_VLINE_INTERRUPT)
> - WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,
> VLINE_ACK);
> + if (rdev->num_crtc >= 4) {
> + if (rdev->irq.stat_regs.evergreen.d3grph_int &
> GRPH_PFLIP_INT_OCCURRED)
> + WREG32(GRPH_INT_STATUS +
> EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
> + if (rdev->irq.stat_regs.evergreen.d4grph_int &
> GRPH_PFLIP_INT_OCCURRED)
> + WREG32(GRPH_INT_STATUS +
> EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
> + if (rdev->irq.stat_regs.evergreen.disp_int_cont2 &
> LB_D3_VBLANK_INTERRUPT)
> + WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
> VBLANK_ACK);
> + if (rdev->irq.stat_regs.evergreen.disp_int_cont2 &
> LB_D3_VLINE_INTERRUPT)
> + WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
> VLINE_ACK);
> + if (rdev->irq.stat_regs.evergreen.disp_int_cont3 &
> LB_D4_VBLANK_INTERRUPT)
> + WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
> VBLANK_ACK);
> + if (rdev->irq.stat_regs.evergreen.disp_int_cont3 &
> LB_D4_VLINE_INTERRUPT)
> + WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
> VLINE_ACK);
> + }
> +
> + if (rdev->num_crtc >= 6) {
> + if (rdev->irq.stat_regs.evergreen.d5grph_int &
> GRPH_PFLIP_INT_OCCURRED)
> + WREG32(GRPH_INT_STATUS +
> EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
> + if (rdev->irq.stat_regs.evergreen.d6grph_int &
> GRPH_PFLIP_INT_OCCURRED)
> + WREG32(GRPH_INT_STATUS +
> EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
> + if (rdev->irq.stat_regs.evergreen.disp_int_cont4 &
> LB_D5_VBLANK_INTERRUPT)
> + WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
> VBLANK_ACK);
> + if (rdev->irq.stat_regs.evergreen.disp_int_cont4 &
> LB_D5_VLINE_INTERRUPT)
> + WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
> VLINE_ACK);
> + if (rdev->irq.stat_regs.evergreen.disp_int_cont5 &
> LB_D6_VBLANK_INTERRUPT)
> + WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,
> VBLANK_ACK);
> + if (rdev->irq.stat_regs.evergreen.disp_int_cont5 &
> LB_D6_VLINE_INTERRUPT)
> + WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,
> VLINE_ACK);
> + }
>
> if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
> tmp = RREG32(DC_HPD1_INT_CONTROL);
