On Thursday, December 4, 2025 3:17 PM Svyatoslav Ryhel wrote: > Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD. > > Signed-off-by: Svyatoslav Ryhel <[email protected]> > Acked-by: Stephen Boyd <[email protected]> > --- > drivers/clk/tegra/clk-tegra20.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c > index bf9a9f8ddf62..9160f27a6cf0 100644 > --- a/drivers/clk/tegra/clk-tegra20.c > +++ b/drivers/clk/tegra/clk-tegra20.c > @@ -801,9 +801,9 @@ static void __init tegra20_periph_clk_init(void) > clks[TEGRA20_CLK_MC] = clk; > > /* dsi */ > - clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, > - 48, periph_clk_enb_refcnt); > - clk_register_clkdev(clk, NULL, "dsi"); > + clk = tegra_clk_register_periph_gate("dsi", "pll_d_out0", 0, > + clk_base, 0, TEGRA20_CLK_DSI, > + periph_clk_enb_refcnt); > clks[TEGRA20_CLK_DSI] = clk; > > /* csus */ >
Reviewed-by: Mikko Perttunen <[email protected]>
